sumit motarwar

DevOps Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in Static Timing Analysis and VLSI design.
  • Proficient in Verilog and Cadence tools.
  • Strong background in SOC design engineering.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in SOC and ASIC development.

Contact

LinkedIn

Skills

Other Skills

VerilogMicrosoft OfficeCadence VirtuosoApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)PerlC (Programming Language)Static Timing AnalysisTCL

About

Currently I am working as SOC Design Engineer at Intel and my work includes timing cleanup at partition and full-chip level.

Experience

6 yrs 9 mos
Total Experience
3 yrs 5 mos
Average Tenure
3 yrs 4 mos
Current Experience

Qualcomm

2 roles

Senior Lead Engineer

Dec 2024 – Present · 1 yr 4 mos

Senior STA Engineer

Dec 2022 – Dec 2024 · 2 yrs

Intel corporation

3 roles

SOC Design Engineer (STA)

Promoted

Aug 2020 – Dec 2022 · 2 yrs 4 mos

CAD Engineer

Aug 2019 – Aug 2020 · 1 yr

Graduate Technical Intern

Jul 2018 – Aug 2019 · 1 yr 1 mo

Education

Vellore Institute of Technology

Master's degree — VLSI design

Jan 2017 – Jan 2019

MGM,Nanded (SRTMUN)

Jan 2012 – Jan 2016

Stackforce found 100+ more professionals with Verilog & Microsoft Office

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