Vaibhavi Tiwari — Software Engineer
Pre-Silicon Verification Engineer | Formal & Functional Verification | Debug IP What I Do • Ensure designs meet spec before they hit silicon - reducing costly iterations • Blend Formal Verification (FPV, SEC for clock gating) & Functional Verification (UVM, debug workflows) • Skilled in Cadence JasperGold & Synopsis Verdi My Background • 🎓 M.Tech in VLSI Design • 📄 IEEE-published research – FPGA & GDS II Performance at WIECON-ECE 2024 Beyond Engineering • 🤖 Mechatronics & 🚁 Drone piloting • 🎹 Certified keyboard player (Trinity College London) - creativity shaping technical thinking Belief Verification isn’t just about 🐞 finding bugs - it’s about ✅ building confidence in every design
Stackforce AI infers this person is a VLSI Design and Verification Engineer with expertise in formal and functional verification.
Location: Bengaluru, Karnataka, India
Experience: 1 yr 11 mos
Skills
- Rtl Design
Career Highlights
- Expert in Pre-Silicon Verification and Debugging IP.
- Published IEEE research on FPGA & GDS II Performance.
- Certified keyboard player enhancing creativity in engineering.
Work Experience
Intel Corporation
Design Verification Engineer (1 yr)
Graphics Formal Verification Intern (11 mos)
Nirma University, Ahmedabad, Gujarat, India
Teaching Assistant (10 mos)
3S MEP + S
Electrical Engineering Intern (6 mos)
Cummins India
Project Intern (1 mo)
Education
Master of Technology - MTech at Nirma University
Bachelor's degree at Adani University
Proficient in AutoCAD at CADD Centre Training Services Private Limited
Diploma at Centre for Development of Advanced Computing (C-DAC)
Initial Electronic Keyboard at Trinity College London
Science (PCM + Biology) at Kendriya Vidyalaya
Science (PCMB) at Kendriya vidyalaya, ONGC Ahmedabad
at Kendriya Vidyalaya, R.K puram, New Delhi
at Kendriya Vidyalaya, Sabarmati, Ahmedabad
at Kendriya vidyalaya, Agartala, Tripura
