Pavan Laxmeshwar

Engineering Manager

Bengaluru, Karnataka, India22 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in fullchip integration and verification.
  • Proven track record in physical design engineering.
  • Expertise in analog and mixed signal IC design.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in IC design and verification.

Contact

LinkedIn

Skills

Core Skills

Fullchip Integration And Verification

Other Skills

Analog and mixed signal IC design

Experience

22 yrs 3 mos
Total Experience
7 yrs 5 mos
Average Tenure
20 yrs 2 mos
Current Experience

Intel corporation

3 roles

Engineering Manager

Promoted

Nov 2021 – Present · 4 yrs 5 mos

Fullchip Integration and VerificationAnalog and mixed signal IC design

SoC Design Engineer

Mar 2015 – Oct 2021 · 6 yrs 7 mos

Physical Design Engineer

Dec 2005 – Feb 2015 · 9 yrs 2 mos

  • Tape-out of multiple chips both products and testchips; handled multiple IP's IC designs

Analog devices

Physical Design Engineer

Dec 2004 – Dec 2005 · 1 yr

  • Supported chip level layouts of ADC's & DAC's

Wipro

Physical Design Engineer

Nov 2003 – Dec 2004 · 1 yr 1 mo

  • Physical design of 90nm IO cells for Texas Instruments