Aug 2022 – Oct 2023 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

• Joined Intel Technology India Pvt. Ltd, Bangalore on 29th August 2022 as FPGA IP Software Engineering Management (India Centre Incharge for FPGA division of TPTD/ATTD) . Responsibility included hiring and building Team, Team ramp up in FPGA RTL(Verilog), FPGA validation (FVAL) for TPTD/ATTD division of Intel India. Delivered multiple features like SCS (serial capture stream), ACD (active channel Depop), HBIDPS Dynamic Ganging etc. Responsibility also included short term and long-term planning of projects along with Intel US headquarter, weekly status reporting to US Headquarter, Team performance management, team trainings, project deliveries, lots of sync up meetings with global teams distributed across India, US, Germany, Malaysia and so on.

Apr 2017 – Aug 2022 · 5 yrs 4 mos

• 1) Software development for our global giant operators(Macro cells) releasing 4 pkgs per year as per 3GPP specs and operators demands. These operators give us several billions of dollars per year. Handling multiple different teams every year which includes DSP teams, MAC Design Team, MAC development Team, RLC/PDCP/GTP teams etc.
• 2) Machine Learning/Artificial Intelligence, Deep Learning knowledge building in team and applying the same for telecom data analytics for issues detection, debugging and intelligence gathering leading to problem solution. Developing a tool for automation using ML/AI .
• 3) Field Issues followup, resolution for our Indian Telecom operator and other Global operators. Issues resolution of isues raised by various testing teams distributed across many countries.
• 4) Team/Project Hiring, Network Group Hiring, Campus Hiring for Samsung India, Interns Hiring, Outsourcing Hiring, Interviewing, collaborating with stakeholders for this.
• 5) Training and soft landing of new hires. Training and continuous learning for the team.
• 6) Collaborating and cowork with Samsung Headquarter in South Korea and other teams distributed globally. Weekly meetings, MOMs, WSR etc.
• 7) Performance management of the teams.
• 8) Vendor/partner/stakeholders management, travelling to other geographies for business purposes.
• 9) Ideas discussions and brainstorming for Papers, Patents, Algorithms and Data structures for Samsung Software Certification Exams for employees.
• 10) Software Quality Management and process improvement to reduce software bugs count in every successive years.
• 11) Other tasks execution as per business needs and priorities.

Jul 2012 – Apr 2017 · 4 yrs 9 mos

• Working in DSP Lab in Network Division R&D Centre at Samsung Electronics Headquarter, South Korea since 16th July 2012.
• Started as Project Leader for Small Cell ENB Software Development work at Samsung HQ. Role involves full responsibility of small cell development.
• Successfully developed 5MHz/10MHz based small cell for US and Japanese operators.
• Team management/collaboration/Co-Work technically for both Korea and Samsung India centre for small cell development.
• Collaboration with Samsung India (SRIB) to Setup a small cell test Lab in SRIB India.
• Interviewing and Hiring team in India as well as in South Korea during initial phase of the project.
• Vendor Management and travelled to US to get the job done from vendor.
• Day to Day Technical issues solving.
• Day to day follow up of issues raised by Operators during field tests.
• Day to day follow up and resolution of technical issues raised by Samsung HQ internal test Labs System Integration Lab (SIT) / System Verification Lab (SVT)/Algorithm Verification Team (AIT).
• Various new feature implementation, Integration and testing.
• System Integration, Verification of MAC protocol Layer and PHY (Modem) Layer with Samsung product and Vendor product.
• Collaboration with other Labs at Samsung HQ for co-work to resolve issues related to multiple Labs.
• Monthly meeting with Vice President/Group Leader (상무/그룹장) for status reporting and discussions.

Nov 2010 – Jun 2012 · 1 yr 7 mos · Bangalore

• LTE-Advance based on 3GPP Rel.10 at Accenture, Bangalore, India: -Responsibility includes Physical Layer Architecture, Design, coding, testing of 3GPP release10 based LTE-Advance. Guiding a team of Engineers for this project. Solving the problems of own modules & modules of my team members. Integration & debugging with the team. Making MOMs, WSRs, Project Planning, Progress tracking, execution and deliveries. Overall responsibility of the project.

Dec 2006 – Nov 2010 · 3 yrs 11 mos · Gurgaon, India and Oulu Finland

• Optimization on starcore DSP for LSI, US at Aricent, Gurgaon, India: - This project involved porting, Assembly Coding and very high degree of optimizations on starcore DSP processor on LSI Boards. C intrinsic and cache enabling were not sufficient to meet the MCPS budget and hence Assembly level coding of selected modules was inevitable to meet the timing requirements. Guided a team of engineers for this. Interaction with customer on weekly basis.
• NSN new BTS (Medusa) software development at Oulu, Finland for Nokia Siemens Networks (NSN) on behalf of Aricent. This project was regarding development of software for new BTS being developed by Nokia Siemens Networks (NSN) at Oulu, Finland. I went to Finland for this work. My responsibility was to develop the software for establishing the communication link between various TI DSPs TI6488 and FPGAs of the BTS using SRIOs. Driver development of peripherals/Interfaces. Verification of various Hardware Accelerators, GSM Frame Timers and various interfaces in between DSPs and FPGAs like SRIO, RP3 etc. Also debugging activities was carried out to find the bugs and convey it to relevant persons. I was also responsible for a lot of coordination among people of various locations like Germany, Finland and India apart from guiding the junior team member for his work.
• LTE Project based on 3GPP Rel8 at Aricent:-
• Studied 3GPP LTE 36.211, 36.212, 36.213, 36.104 specifications. Implementation for FDD as per 3GPP Rel8 specs (36.211, 36.212, and 36.213) of 3GPP LTE for various types of channels and scenarios. MATLAB model was created for selected modules and implementation was done using C Language.
• Worked on Physical Layer group at Aricent for WiMax (802.16e) Technology.

Nov 2005 – Dec 2006 · 1 yr 1 mo · Bangalore

• Worked on Physical Layer design and development of MIMO-OFDM based wireless LAN (802.11n) project at Esqube Communications, Bangalore, India. Responsibility included system level design along with team, my own unit level design, RTL coding in Verilog based on MATLAB Model for modules like Encoder Parser, MCS Decoder, Shared memory interfaces for TX and RX, Parallel to serial and serial to parallel conversion, various FIFOs, Windowing and Cyclic Prefix Logic, Scrambler, Convolutional Encoder. Integration of whole TX chain and debugging.
• Worked on Navini-WiMax Project of Navini Networks, US, Dallas for Physical Layer Implementation of CPE side of Navini-WiMax at Esqube Communications, Bangalore, India. This was a very fast paced work and we had to give daily status to the client. We were 5 members of developers and we were reporting to Manager, Navini Networks, US, Dallas on day to day basis.
• Role Played:-
• (1) Implemented Tail Bite Viterbi Decoder on TI DSP (TI320C55X) for Navini Networks WiMax Project
• (2) Made test cases document for Navini WiMax Project
• (3) Setting up of peripherals for WiMax CPE of Navini Networks. The board contained 3 DSP Processors (TI-OMAP5910, and two TI320C55X DSP Processors).

Jan 2004 – Jan 2005 · 1 yr · Hyderabad Area, India

• 14.4 kbps Modem design and implementation on TI320C54x DSP on behalf of Danlaw Technologies India Ltd, Hyderabad for Indian Space Research Organization (ISRO) for satellite communication applications.
• No. of members: - 2
• Role Played: - Designed the Modem Architecture. Simulation using MATLAB. ‘C’
• Callable Assembly Coding on TI DSP (TI320C54X DSP), Peripherals settings (McBSP, DMA, Timer etc using the various registers) Viterbi Decoder, various filters, Costas loop for carrier recovery etc. Project delivered to ISRO
• VLSI Architecture Design and its FPGA implementation for FM Tape speed Compensation on behalf of Danlaw Technologies India Ltd for Hindustan Aeronautics Limited(HAL), Bangalore
• No. of Members: - 2
• Language Used: - MATLAB, VHDL
• Role Played: - Designed the methodology for tape jitter compensation using DSP methods like decimation, filtering and other modules and simulation of the technique in MATLAB to verify the functionality. Guided the other member of another department for RTL coding and verification till the product was delivered to the customer.
• 9.6 kbps Modem design and implementation on TI320C54x DSP for ISRO for satellite communication.
• Adaptive Filter based Noise Cancellation using statistical signal processing algorithm (LMS, NLMS) for line echo cancellation.