Jul 2025 – Present · 9 mos

• AI SOC Engineering

Apr 2024 – Jul 2025 · 1 yr 3 mos

Apr 2019 – Mar 2024 · 4 yrs 11 mos

• FE MANAGER/LEAD (XEG-I) SOC ORG
• 3 SOC servers including Clearwater Forest- the First 3D stacked server.
• Responsibilities: -.
• Lead/Technical Management
• Set up, Recruit and Build the FE (rtl+val) org
• SOC Org- 1->35 Design Engineers across grades in 2 years (2019-2021).
• IP Org - 2->24 Design Engineers across grades in 3 years(2016-2019).
• Drive SOC rtl integration, model build, SOC reset bring up to the first code fetch. Deliver SOC rtl model and enable downstream stake holders – Pre Si Val, BE, Emul.
• As part of SOC FE implementation drive the following - IP Integration, SOC fabrics, UPF & CDC, DFT, Power intent design, Clock, Reset, Fuses, Design Partitioning, RTL Quality check and signoff leading to quality BE implementation.
• Work with architecture team on SOC high level arch, uArch definition, IP requirement and deliverables.
• Contribute to Bounding box analysis, Design, Verification, Test-plan, Timing Convergence & Floorplan, Tape-out Signoff.
• Contribute to the group working on optimal product Floor Plan and accommodate those requirements in FE model even from day 0.
• Drive HW bug management between generations and chops, take them through DCCB, implement and drive them to closure through stake holder management to enable Tape In and PRQ.
• Run scrums, stand-up meetings and regular execution sync meetings with stake holders to resolve bottlenecks & ensure On time execution.
• Actively manage schedule, deliverables, risk and mitigation options.
• Participate in leadership sync with business group VPs and present status on progress, challenges, and customer feedbacks.
• Support the broader Power-On activities by providing Tech leadership in Debug Domain. Drive the Post Si bug – Debug and closure by working with the design and val engineers across Geos.
• Org Management .
• Drive the culture of innovation, product excellence and consistent strong execution.

Nov 2014 – Jul 2016 · 1 yr 8 mos

• DFD Architect for the next gen server SOC
• As SOC DFD architect drove the DFD through Path finding and TR activities. Came up with the SOC DFD architecture by working with global PE (Principal Engineers) and SS (subsystem) leads. Worked with external stake holders to understand the DFD within their HIP and designed DFD block in the 3 new subsystems that integrate agent into the SOC. Have been driving DFX val efforts for SOC.
• Val Lead for DFD IPs from BDC
• As DFD Val lead have been driving val execution for the 4 IPs designed out of BDC. Drove the val complexity, effort estimation, val strategy + task list compilation for IPs from Bangalore. Working with subsystem team for integration of our IPs into their env and subsequent validation.
• Brought up the OVM / SAOLA based val env from grounds up for one IP and helped bring up other IPs. SDG India LV site training champion
• As SDG BDC site single point of contact for all LV trainings, coordinated cross site LV trainings with central training team. Served as SDG India representative in BDC site training champions forum and helped deliver several technical skill development trainings.
• Delivered the LV training for 14+ new validation employees by coordinating activities between trainers, logistics and trainees. It was well received and appreciated through excellent feedback.

Apr 2014 – Mar 2019 · 4 yrs 11 mos

• DEBUG IP FE LEAD/MANAGER (XIG) MARCH 2014-MARCH 2019
• Owned Uarch, implementation and SoC execution.
• Delivered several Debug IPs across generations used in Client and Server SOCs.
• Participate in IP Architecture and Design WGs that arrive at IP landing zone requirements.
• Drive rtl coding, implement and signoff the rtl quality tool requirements, Drive new val test plan creation and its execution.
• Drive IP integration support to SoC customers and represent IP team in bug disposition of Lead SOCs.
• Owned High-level schedule and responsible for day2day SoC execution activities.
• Co owned the Debug Architecture and Drove the SOC level Debug Val COE for all India site owned products ( 4 server SOCs) – set up Matrix Org for this work – 12 Val Engineers reported to this org.
• Post Si Validation
• Design/PVE Support – As part of Debug SLD was actively involved during the “Power On” activities of micro server and main line server project. Supported the PVE team in their power on and tool check out tasks by actively taking the IOT, NOA, Visa and Trigger (MBP, Lakemore) traces. These traces were used to identify the power on blocking issues. Root caused and identified correct fix (row inversion) for KR visa bring up. This helped in checkout of KR which was a major milestone in PVE.
• Helped in several critical siting debug for both microserver and main line server product - by creating of ittp, comet check-in, vcf conversion and correctness checkout in Tester. These were done on the fly, through several iterations until the root cause was identified and issues were resolved.

Jan 2011 – Nov 2014 · 3 yrs 10 mos

• Pre-Si DFX Validation, Product –22nm, 14nm next gen Server
• As a DFD val lead for 14nm Xeon MicroServer/Server designed from Bangalore, was responsible for defining and validating the feature level test plans at uncore level. As part of TR, worked with the rtl code owners to come up with validation complexity and effort estimation, collateral changes for these new features to be validated. Led the system debug efforts from DFX side and came up with use case model validation in Pre-Si environment. Validated 5 new features by writing several directed/randomized tests, checkers/monitors.
• Integrated several debug IP Modules into SOC and validated the debug features of entire South Complex for Intel’s first Xeon Microserver(14nm).
• Owned the Pre-Si Validation of Trigger and Design For Debug(DFD) features for the 22nm Server Product. Developed Test Plan, wrote new directed/randomized tests, checker and monitor, worked with Post silicon system debug team to come up with use case validation. Contributed heavily to greater fuse end point validation through scripts etc.

Jun 2004 – Apr 2011 · 6 yrs 10 mos

• Led the Post Si Debug Test Lab team for 2 projects in Bangalore and contributed heavily for projects in US.
• Led a team of 25 Engineers and technicians spread between India and Malaysia in the Post Silicon Validation areas of Speed and General Debug, Mass Data Collection, Results Management.
• Led a group of 10 engineers spread between US and India, in the development of Design for Test (DFT) tools, Automation Flow, Results Management tools and ensured their delivery on time for the first silicon.
• Mentored and Trained 35 Engineers from design/debug teams on Speed debug methodology, Result Management, DFT Tools usage models.
• Owned the development and execution of 40+ DOE that identifies speed path and possible electric circuit fix to increase speed of microprocessor.
• Served as a key contributor in finalizing the usage models of DFT tools. Contributed to general debug and developed automation scripts for Mass Data Collection on multiple ATEs for speed debug.