Vishnu Priya Bitra

Software Engineer

Bengaluru, Karnataka, India9 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in CPU architecture and verification engineering.
  • Proven track record in developing innovative verification tools.
  • Hands-on experience with pre-silicon validation and debugging.
Stackforce AI infers this person is a Verification Engineer specializing in CPU architecture and pre-silicon validation.

Contact

Skills

Core Skills

Verification EngineeringCpu Architecture

Other Skills

UVMLoad/store Design verificationPaging/MMU feature developmentAddress generator component developmentMemory attributesHypervisorRTL verificationStimulus generationC++DebuggingCoveragePerl scriptingAVFDebugging CPU RTLAMD x86 microarchitecture

Experience

9 yrs 2 mos
Total Experience
1 yr 11 mos
Average Tenure
1 yr 5 mos
Current Experience

Qualcomm

Senior Lead Engineer

Nov 2024Present · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

Tenstorrent

2 roles

Senior Verification Engineer

Promoted

Jun 2023Nov 2024 · 1 yr 5 mos · Bengaluru, Karnataka, India

  • Working in Load/store Design verification team for RISC-V high-performing out-of-order CPU. This is a from-scratch design in UVM.
  • Responsible for entire Paging/MMU feature development including stimulus, checkers,coverage, debug and fixes.
  • Developed entire address generator component from scratch which includes memory setup, page table generation, pages and address generation to hit all possible scenarios of different features.
  • Worked passively on other features including memory attributes, hypervisor.
  • Have a decent understanding of Load/Store block arch and micro-arch.
UVMLoad/store Design verificationPaging/MMU feature developmentAddress generator component developmentMemory attributesHypervisor+2

Engineer

Apr 2022Jun 2023 · 1 yr 2 mos · Bengaluru, Karnataka, India

Amd

3 roles

Senior silicon design engineer

Nov 2021Apr 2022 · 5 mos

Silicon Design Engineer 2

Promoted

Jun 2019Dec 2021 · 2 yrs 6 mos

  • Load/Store unit pre-silicon RTL verification team for Zen 5 architecture.
  • Includes stimulus generation, coding checkers using AVF, C++ and UVM, debugging and coverage.
  • Core level Verification
  • worked in developing an innovative took to improve pre-silicon debug efficiency for Zen 3 architecture
RTL verificationStimulus generationC++UVMDebuggingCoverage+2

Silicon Design Engineer 1

Apr 2018Jun 2019 · 1 yr 2 mos

  • CPU pre-silicon Verification team for Zen 3 architecture
  • good RTL verification and debugging skills
  • worked on PMC validation of Load/Store unit events.
  • hands-on experience in perl scripting, C++ and AVF(AMD verification tool)
  • worked as part of Load/Store verification team which includes RTL debugging, coverage and stimulus generation.
  • good AVF(analogous to UVM), C++ and testbench knowledge.
RTL verificationDebuggingPerl scriptingC++AVFVerification Engineering+1

Verifiq technologies private limited

Verification Engineer

Jun 2017Mar 2018 · 9 mos · Bangalore

  • Worked for AMD as a part of CPU verification team which includes debugging CPU RTL at core level
  • Good understanding of AMD x86 microarchitecture.
Debugging CPU RTLAMD x86 microarchitectureVerification Engineering

Arm

Internship

Jan 2017Jun 2017 · 5 mos · Bengaluru Area, India

  • Worked on SoC RTL pre-silicon system analysis and benchmarking mobile and infra systems. Have hands on debugging waves using verdi, instruction trace and bus logger traces.
  • Good understanding of performance concepts like latency and bandwidth, SoC architecture, system testbench, AXI 4, CHI protocols, industry standard baremetal benchmarks, SPEC 2000 benchmarks
SoC RTL pre-silicon analysisDebugging wavesInstruction traceBus logger traces

Indian institute of technology, madras

Winter Intern

Dec 2015Jan 2016 · 1 mo · Chennai Area, India

  • Study on Wireless Power Quality Meter- ELSPEC Black Box G4500, IIT Madras
  • The aim of the project was to get acquainted with the Power quality meter, configuring a Remote Display unit for monitoring real time values and set it up for usage through Local Area Network. The device’s working and the theory associated with the monitoring of electrical networks is analyzed.
Power quality meterRemote Display unit configuration

Csir-ceeri

Intern

May 2015Jul 2015 · 2 mos · Chennai Area, India

  • Sorting different kinds of plastic using NIR spectroscopy based Plastic Sorting Device
  • The main aim of the project is to identify highly efficient algorithm for the device. We have collected online data of 5000 samples of variety of plastics and implemented Support Vector Machine algorithm which resulted in 98% efficiency
NIR spectroscopyPlastic sorting algorithm

Education

Purdue University

Master of Science - MS — electrical and computer engineering

Aug 2021Dec 2025

Birla Institute of Technology and Science, Pilani

Bachelor of Engineering (B.E.) — Electrical and Electronics Engineering

Jan 2013Jan 2017

Ongole Public School, Ongole

class 10 — ICSE

Jan 2005Jan 2011

Stackforce found 11 more professionals with Verification Engineering & Cpu Architecture

Explore similar profiles based on matching skills and experience