Rajesh Devaraj

Software Engineer

India17 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in kernel mode device driver development for GPUs.
Published research on real-time systems and scheduling.
Extensive experience in FPGA/ASIC verification.

Stackforce AI infers this person is a highly skilled engineer in System Software and FPGA/ASIC verification within Aerospace and Consumer Electronics.

Contact

Skills

Core Skills

System Software EngineeringResearch And DevelopmentScheduler DesignFpga/asic Design And Verification

Other Skills

kernel mode device driver developmentGPUReal-Time SystemsResearchFPGAASICVHDLVerilogSystem VerilogTest-bench developmentDebugging RTL IssuesFailure Mode and Effects Analysis (FMEA)CData Structures

About

Working as a Senior System Software Engineer at Nvidia. Obtained Dual-Degrees (M.Tech. + Ph.D.) in Computer Science from IIT Guwahati. Earlier, worked at HCL Technologies as a VLSI professional. Research interests include Scheduler Design for Real-Time Systems, Fault-Tolerant Computing. In the area of computing systems, reviewed research articles from IEEE/ACM/Elsevier/Springer/Wiley, for more than 850 times.

Experience

17 yrs 10 mos

Total Experience

6 yrs

Average Tenure

7 yrs 8 mos

Current Experience

Nvidia

Senior System Software Engineer

Sep 2018 – Present · 7 yrs 8 mos · India · Remote

Involved in kernel mode device driver development for GPU, as part of SW-TEGRA.

kernel mode device driver developmentGPUSystem Software Engineering

Indian institute of technology, guwahati

Research Scholar

Jul 2012 – Dec 2018 · 6 yrs 5 mos · Guwahati Area, India

Dual Degrees (M.Tech. + Ph.D.) in Computer Science.
M.Tech.: July 2012 to June 2014; Ph.D.: July 2014 to December 2018.
Thesis title: "Real-time Scheduler Design for Safety-critical systems: A Supervisory Control Approach"
Link: https://shodhganga.inflibnet.ac.in/handle/10603/473256#
Guide: Prof. Arnab Sarkar, IIT Kharagpur ( http://www.facweb.iitkgp.ac.in/~arnab/ )
Co-Guide: Prof. Santosh Biswas, IIT Bhilai ( https://www.iitbhilai.ac.in/index.php?pid=santosh )
Nominated for ACM India Doctoral Dissertation Award (2020) by the Dept. of CSE, IIT Guwahati.
Google Scholar Page: https://scholar.google.co.in/citations?user=2YgXwZsAAAAJ&hl=en&oi=ao
DBLP: https://dblp.org/pid/174/1458.html
ResearchGate: https://www.researchgate.net/profile/Rajesh-Devaraj
Web of Science: https://www.webofscience.com/wos/author/record/J-1984-2019
Orcid: https://orcid.org/0000-0002-4481-102X

Scheduler DesignReal-Time SystemsResearchResearch and Development

Hcl technologies

Member Technical Staff

Jul 2008 – Jul 2012 · 4 yrs · Chennai Area, India

Worked as FPGA/ASIC Front-end RTL (pre-silicon) Verification Engineer in Aerospace (Flight Control Systems) and Consumer Electronics (Un-manned Vehicle, Multi-Function Printers) related projects.
Hands-on experience in Test-bench development using VHDL, Verilog and System Verilog. Familiar with EDA tools like Cadence NC-SIM, Modelsim, Synopsys VCS, TransEDA. Involved in the preparation of artifacts for SOI-3 (Stage of Involvement-3) audit for Aerospace related projects.
Area of expertise includes Requirements Analysis, Test Plan Preparation, Test-bench Development (system level as well as unit level), Debugging RTL Issues, Coverage Analysis.
Worked for Various clients: Flight Control Systems Division of Parker Aerospace, GE Oil & Gas, Hamilton Sundstrand, Xerox Inc.

FPGAASICVHDLVerilogSystem VerilogTest-bench development+2