Jan 2015 – Dec 2018 · 3 yrs 11 mos · Greater Phoenix Area

• Optimize and analyze complex enterprise software implemented in . Identified software hotspots using profiling tools such as Intel VTune and Linux perf.
• Debug performance bottlenecks of software and hardware using performance monitoring counters and Linux performance tools to deliver performance collaterals and workload characterization reports. Develop and direct performance and software readiness validation on emerging Intel memory technology to discover software and hardware glass jaws.
• Enable key customer software on SIMICS; a full system simulator; to advance customer software development on future Intel products using software shift left. Organize deep technical collaboration with Intel partners to provide data driven analysis and recommendations for future Intel product features.
• Closely collaborate with performance marketing team to design and execute competitive benchmarking experiments on Intel and competing platforms. Develop several small software utilities using Python and shell scripting to automate data collection and post-process performance data.

Jun 2014 – Dec 2014 · 6 mos · Greater Pittsburgh Region

• Designed a debugging system for Blinky Blocks( http://www.cs.cmu.edu/~claytronics/hardware/blinkyblocks.html ) at Claytronics lab ( http://www.cs.cmu.edu/~claytronics/ ) and developed front-end and backend software
• Developed APIs for command propagation and debug information retrieval from Blinky Blocks using C and C++
• Developed software in C for handling of frontend requests, querying Blinky Blocks and generating responses
• Designed the Front-End Interface of the debugger using HTML5, CSS and the JQuery JavaScript library.

May 2011 – Jul 2013 · 2 yrs 2 mos · Greater Hyderabad Area

• Developed firmware for the Wi-Fi Medium Access Control (MAC) data communication protocol packet processing in C and Assembly level language. Helped in design, implementation and unit-level validation, bug fixing for new feature development in a Wi-Fi SOC subsystems using Verilog
• Performed Pre-Silicon validation of various hardware subsystems using simulation and formal verification tools
• Designed constrained randomization test bench software in System Verilog using the VMM methodology to catch hardware and firmware bugs. Debugged hardware and software issues during pre and post-silicon validation. Created scripts to run simulations/regressions, extensively debugged regression failures