Madhusudan Govindarajan

Director of Engineering

Bengaluru, Karnataka, India18 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ADC design with a focus on low power solutions.
  • Led multiple Analog Front End projects for advanced communication standards.
  • Proven track record in Power Management IP design.
Stackforce AI infers this person is a Semiconductor Design Engineer specializing in Analog Circuit Design and Power Management.

Contact

LinkedIn

Skills

Core Skills

Analog Circuit DesignAdcsPower Management

Other Skills

ADC designAnalog Front Endlow power designlow area designAsynchronous SAR ADCPipelined ADCCapless LDOPower-ON-Reset CircuitSynchronous SAR ADCBehavioural Verilog modellingSoCAFEIntegrated Circuit DesignVirtuosoCircuit Design

About

Analog Design Engineer with expertise in ADC design. I design Asynchronous and Time interleaved SAR ADCs and High Speed Pipelined ADCs. I have also Designed Capless LDO and POR as part of Power management IPs. I have led Analog Front End IP projects for Wi-Fi / WiMAX and LTE Applications. I have also led Power Management IP projects for Flash Memory Applications

Experience

18 yrs 6 mos
Total Experience
4 yrs 7 mos
Average Tenure
8 yrs 8 mos
Current Experience

Samsung india

3 roles

Director

Promoted

Mar 2025 – Present · 1 yr 2 mos

Associate Director

Promoted

Mar 2021 – Feb 2025 · 3 yrs 11 mos

Sr Staff Design Engineer

Jul 2017 – Feb 2021 · 3 yrs 7 mos

Maxlinear

Sr Staff RF/MS IC Design Engineer

Dec 2015 – Jun 2017 · 1 yr 6 mos · Bengaluru Area, India

Cadence design systems

Principal Design Engineer

May 2013 – Nov 2015 · 2 yrs 6 mos · Bengaluru Area, India

  • Design of SAR based ADC for LTE and LTE-A Analog Front End with target ultra low power and low area
ADC designAnalog Front Endlow power designlow area designAnalog Circuit DesignADCs

Cosmic circuits

2 roles

Project Lead - AFE

Promoted

Apr 2010 – May 2013 · 3 yrs 1 mo

  • Designed Asynchronous SAR based Dual ADC for Wi-Fi / WiMAX Analog Front End with ultra low Power and Area in 65nm and 40nm nodes
  • Designed Pipelined Based Dual ADC for LTE Analog Front End in 65nm and 40nm nodes
  • Designed Capless LDO, Power-ON-Reset Circuit
  • I have led Analog Front End Design for Wi-Fi / WiMAX
  • I have led Power Management Macro Design (LDOs, PORs, Osc) for Flash Memory application
Asynchronous SAR ADCPipelined ADCPower ManagementCapless LDOPower-ON-Reset CircuitAnalog Circuit Design

Design Engineer

Jul 2007 – Mar 2010 · 2 yrs 8 mos

  • Designed Synchronous SAR based Dual ADCs for Wi-Fi / WiMAX Analog Front End
  • Behavioural Verilog modelling of Analog Front End to enable SoC designers to simulate and verify the integration of the AFE in the SoC
Synchronous SAR ADCBehavioural Verilog modellingAnalog Circuit Design

Education

PESIT, Bangalore

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2003 – Jan 2007

Sadvidya PU College, Mysore

PUC — Science

Jan 2001 – Jan 2003