Deepak Garg — Software Engineer
16+ years of experience in ASIC Design & Verification for wireless IPs. Experience in system level analysis, H/W - S/W partitioning, Design, Verification and Validation support of H/W accelerator sub-modules implementing the advanced receiver algorithms for LTE wireless Modem. Specialties: ASIC design & verification for wireless domain. Verilog, VHDL, System Verilog, PERL, C++ Good understanding of ASIPs & their design. Good understanding of 3GPP LTE physical layer specification and receiver channel estimation & detection algorithms for wireless communication systems. Hardware-Software partitioning & system level analysis of Layer 1 for LTE baseband modem. Expertise in development of Testbench architecture, Verification plan & Testbench using UVM
Stackforce AI infers this person is a Wireless Communications expert with extensive ASIC design and verification experience.
Location: Bengaluru, Karnataka, India
Experience: 17 yrs 1 mo
Skills
- Asic Design & Verification
- Wireless Communications Systems
Career Highlights
- 16+ years in ASIC Design & Verification.
- Expert in LTE wireless modem technologies.
- Proficient in UVM and testbench architecture.
Work Experience
Qualcomm
Engineer, Sr Staff/Mgr (5 yrs 4 mos)
Engineer, Staff/Mgr (2 yrs 11 mos)
Lead Engineer, Sr (2 yrs 6 mos)
Senior Engineer (1 yr 7 mos)
Renesas Mobile Corporation
Senior Design Engineer (2 yrs 8 mos)
Nokia
Design Engineer (1 mo)
Mirafra Technologies
Design Engineer (6 mos)
Xilinx
Associate Engineer (1 yr 7 mos)
University of New Mexico
Intern (2 mos)
Education
B.Tech & M.Tech at Indian Institute of Technology, Madras
Senior Secondary at Maheshwari Public School, Jaipur