T

Tejaswini Gummadavelly

Software Engineer

Bengaluru, Karnataka, India4 yrs 1 mo experience
Highly Stable

Key Highlights

  • Experienced in subsystem verification methodologies.
  • Proficient in digital design and verification languages.
  • Strong foundation in electronics and communications engineering.
Stackforce AI infers this person is a Design Verification Engineer with expertise in digital design and verification methodologies.

Contact

Skills

Core Skills

Subystem Verification

Other Skills

Digital DesignsVerilogSystemVerilogUniversal Verification Methodology (UVM)Assertion Based Verification

Experience

4 yrs 1 mo
Total Experience
4 yrs 1 mo
Average Tenure
4 yrs 1 mo
Current Experience

Mediatek

2 roles

Senior Design Verification Engineer

Promoted

Jan 2025Present · 1 yr 3 mos · Bengaluru, Karnataka, India

Subystem verification

Verification Engineer

Mar 2022Jan 2025 · 2 yrs 10 mos · Bengaluru, Karnataka, India

Subystem verification

Maven silicon

Trainee

Oct 2021Mar 2022 · 5 mos · Bengaluru, Karnataka, India

Education

Vidya Jyothi Institute Of Technology

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2017Jan 2021

Tejaswini Gummadavelly - Software Engineer | Stackforce