Manish Jindgar

CTO

India19 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

19 years of experience in end-to-end product development.
Expertise in firmware and OS enablement for various architectures.
Proven leadership in Time Sensitive Networking technology.

Stackforce AI infers this person is a highly skilled Embedded Systems Engineer with a focus on Automotive and Industrial applications.

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Skills

Core Skills

Firmware EnablementTime Sensitive NetworkingVision ProcessingMachine LearningSignal ProcessingEmbedded Software

Other Skills

BIOS enablementSlim boot loader supportAudio framework enablementYoctoUbuntuVxworksBoot loaderE2E SolutionsReal-time computingARM architectureDebuggingCloud servicesVision processing algorithmsRADAR technologyDriver Information systems

About

19 years of work experience across End to End product development stages starting from platform design (validation platforms, customer platforms), Firmware enablement (Bare metal, SBL/U-boot and BIOS), OS enablement (BSP porting for Linux, Zephyr RTOS, FreeRTOS) and application enabling encompasses various technologies like Time Sensitive Networking (TSN), Sound Open Firmware, Qt framework etc. The work contributed at various stages of product lifecycles like SoC architectures design phase (ARM, PPC and x86), feasibility analysis (KPIs and identify bottlenecks), system level validation, software & firmware enabling and customer support. The journey so far provided exposure to Automotive, Industrial and Consumer domain solutions.

Experience

19 yrs 7 mos

Total Experience

4 yrs 11 mos

Average Tenure

7 yrs 4 mos

Current Experience

Intel corporation

Software Enabling and Optimization Lead

Dec 2018 – Present · 7 yrs 4 mos · Delhi, India · Remote

Responsibilities
BIOS enablement for Core and Atom series products (DRAM, PCIe devices, Audio etc)
Slim boot loader support for APAC customers (DRAM, PCI devices, Audio, etc)
Global lead firmware enablement for ARM Cortex-M7 based engine (Intel ® PSE) in Intel Atom® x6000E series IOT chipset
Enablement of audio framework, A/V over HDMI, eSPI bridges etc over Yocto, Ubuntu, Vxworks
Technology lead for Time Sensitive Networking (802.1AS, Qbu, Qav, Qbv, Qbr) and Time Coordinated Computing (Intel ® TCC) technology for Yocto/Ubuntu OS
Projects Undertaken:
o Boot loader and E2E Solutions lead for APAC customers
o Global lead for Time Sensitive Networking (TSN) and Real time (Time coordinated Computing- TCC) enabling for Intel® Core, Atom and Xeon platforms
o Enablement of ARM based engine (Intel® PSE) in Intel Atom® x6000E series
 Platform lead for Zephyr based firmware on ARM engine
 Drive use case validation for key features supported by Intel® PSE engine
 Drive Enabling Ethernet use case like Wake on LAN using Integrated Mac and Discrete Ethernet over PCIe
 Enabling Out of Band (OOB) services via cloud (Azure, Telit, Thingsboard)
 KPI definition and measurements for ARM engine
 Debug & development ecosystem support (LTB, Ulinkpro, OpenOCD, Dstream-ST)
 Drive customer documents with certification for enhanced User Experience
 Customer training and support
o Enablement of Security framework for ARM engine firmware deployment and Debugging
 Secure firmware deployment using RSA 3K & SHA 256 encryption via UEFI BIOS
 Enabling interaction with Intel® Converged Security Engine for Unlocking the secured ARM CoreSight ecosystem for invasive debug using tokens (OEM/ODM)
 User experience on ease of usage for firmware deployment/unlocking for ODM/OEM partner during development phase

BIOS enablementSlim boot loader supportFirmware enablementTime Sensitive NetworkingAudio framework enablementYocto+2

Samsung electronics

Senior Product Development Manager

Aug 2017 – Nov 2018 · 1 yr 3 mos · Noida Area, India

Responsible for next generation visual display portfolio

Nxp semiconductors

Lead Application Engineer at NXP India

Jul 2008 – Aug 2017 · 9 yrs 1 mo · New Delhi Area, India

Lead application engineer at NXP India. Contributed on variety of domains likes Vision processing algorithms for ADAS systems, Machine learning (SVM & ANN), RADAR technology for ADAS systems, Driver Information systems, Graphics systems, Audio/Video domain etc.
ADAS Vision assisted driving project based on ARM based S32V234 Processor
Traffic sign recognition application based on HOG (Histogram of Oriented Gradients) algorithm
Pedestrian detection application based on HOG algorithm
Linear SVM used for the machine learning
Lane departure warning using Hough transform
Artificial Neural Networks for machine learning
RADAR technology for ADAS domain based on S32R device
Fundamentals of RADAR technique, usage of FFT, CFAR and KALMAN algorithms
Signal processing toolbox (FFT modules to obtain distance, velocity and Azimuth of an object)
Hardware design know how comprising of 77GHz antenna and analog front end
High end Automotive cluster based on ARM based MAC57Dxxx controller
Architect the hardware comprising of SDR memory, TFT LCD, GPU, Stepper motors, camera interface (ITU656)
Software application using light weight scheduler showcasing navigation screen, music player, phone book profile etc
Automobile Infotainment system based on ARM based VFxxx processor
Linux based application using Qt framework providing feature like music player, GPS, FM radio,
Reverse parking assist and Bluetooth connectivity
Developed Drivers for the camera interface
Architect the hardware design comprising of DDR3, SDHC, USB, FM antenna, GPS antenna, dual TFT LCD, audio(I2S) & camera support (ITU656)
Ported the Linux BSP
HVAC solutions based on PowerPC based MPC5645S controller
Light weight OS based application comprising of features like climate control, touch screen
and IR remote control based user control for air conditioning
Architect the hardware design comprising of QSPI, TFT LCD, audio(I2S) & camera support

Vision processing algorithmsMachine learningRADAR technologyDriver Information systemsGraphics systemsAudio/Video domain+1

Centre for development of telematics (c-dot)

Research Engineer

Aug 2006 – Jul 2008 · 1 yr 11 mos · New Delhi Area, India

Responsible for Transponder board design for 2.5 GBPS and 10 GBPS for telecom backbone.
Worked on the MPC860 and MPC8260 processors

Education

Netaji Subhas Institute of Technology

Bachelor of Technology - BTech

Jan 2002 – Jan 2006

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