Sep 2022 – Present · 3 yrs 7 mos · Bengaluru, Karnataka, India

• Firmware engineer

Feb 2021 – Sep 2022 · 1 yr 7 mos

• Led technology execution for timely, high-quality delivery of multiple post-production Intel Server platforms through IPU (Intel Product Updates), with responsibility spanning validation architecture and debug of critical issues across UEFI BIOS, microcode, and other SoC firmware components.
• Drove resolution of multiple complex, showstopper customer issues that blocked unit shipments and caused line-down situations, leading platform-level investigations across manufacturing, firmware, and software domains in post-silicon environments.
• Developed strong expertise in multi-socket server platforms (2S/4S/8S), RAS, and SoC security technologies including ACM, Boot Guard, TXT, and TPM, along with deep understanding of PCIe, memory ECC, and ADDDC-based reliability mechanisms.
• Defined validation architecture and coverage for high-priority PRT issues, with particular focus on security-related problem areas and platform robustness.
• Built, scaled, and mentored a team of 20+ engineers, successfully delivering validation and debug support for more than 10 IPU platforms within a year.

Mar 2019 – Jan 2021 · 1 yr 10 mos

• Built deep expertise across the full chip/SoC lifecycle, from first power-on to production deployment, working across hardware, firmware, system software, application stack, and manufacturing domains.
• Drove bring-up of a new SoC platform and established stability within weeks of power-on, achieving zero failures across 2,000 reset cycles through cross-functional debug and resolution across SoC, FPGA, BIOS, and board components.
• Partnered with internal and external stakeholders to root-cause and resolve several milestone-critical SoC issues, helping keep program execution on track.
• Developed practical experience in deploying AI inference SoC platforms at scale in data center environments, including OCP systems, OpenBMC-based manageability, ResNet-50-class workloads, and PCIe endpoint stability and compliance.

Jun 2017 – Mar 2019 · 1 yr 9 mos

• Chromebook is a Chrome browser-based laptop built on top of all open-source components like Linux kernel, Coreboot open-source BIOS, embedded controller firmware etc.
• Identifying critical gaps on IA based Chrome product line and define architectural solutions to address them. One of them enables MRC (Memory Reference Code) update in field which helps update critical memory related fixes in the field saving recalls.
• Other work involves architecture definition for In field firmware update flows for security engine as well as microcode on IA platforms.
• Good understanding of Secure boot flows on Chrome platform which involves SoC RoT (Root of Trust: CSME + Boot guard), Verified boot flows (Coreboot) and platform level security features (Google Titan).
• Hands on knowledge on Intel BIOS FSP: Firmware Support Package and worked on early definition of the same.
• Solid understanding of overall platform level architecture of Chromebooks with hands on debug.

Jun 2014 – Jun 2017 · 3 yrs

• Built a team of Coreboot BIOS engineers at Intel from scratch and mentored them to System BIOS flows and lead delivery of multiple generations of Chromebook based on Intel Core SoCs.
• Key stakeholder in enabling FSP interface to Coreboot/Chrome firmware for first big core platform which now ships as default in millions of Chrome devices.
• Hands on experience resolving multiple BIOS issues around ACPI, Power management, SMM and Silicon initialization flows.
• Deep understanding of Coreboot: build environment/architecture flows/romstage/ramstage/payloads etc.
• Understanding of Linux kernel/driver and its boot flows.

Feb 2011 – Jun 2014 · 3 yrs 4 mos

• The sensor hub is an IP part of Intel SoCs which was introduced to apply sensor fusion at co-processor level and apply smart filtering to save power on main CPU.
• Part of the team that conceptualized the sensing IP and drove it till production.
• Lead architectural definition of this new IP. This involved understanding performance/power requirements and based on that define cache size/cpu freq requirements for the IP.
• Built a team that delivered x86 firmware for the IP.
• Involved in definition for Sensor Core firmware for ISH as well as rest of the firmware stack (RTOS).
• Developed HID (human interface device) interface for ISH to interface with OS.

Jan 2009 – Oct 2010 · 1 yr 9 mos

• Build a new technical charter for 3D graphics and build a new team.
• Lead a team of 3D graphics driver developers working in pre-Si SLE environment
• Debugging performance issues in pre-si environments.
• Windows driver debug

Feb 2004 – Jan 2011 · 6 yrs 11 mos

• Hand on board/chipset bring up of more than 8-10 Intel Centrino platforms.
• UEFI BIOS as well as assembly level experience.
• Lead a team of system BIOS engineers.
• Intel CPU power management (C-states, P-states and Clock gating architecture).
• Good understanding of PCI, PCI-Express, USB, Graphics and other chipset architectures.
• Hands on debug system BIOS issues and drive them to closer
• Program management of world wide system BIOS program spread across globe
• Mentor new joiners and build a team from scratch

Jan 2004 – Jan 2011 · 7 yrs

• Zigbee based smart lighting solution which includes sensor nodes as well as raspberry Pi based gateways and Amazon cloud based end to end system.
• Smart street lighting and Smart office lighting system design and deployments
• Zigbee based smart home which includes occupancy, push button, smoke detector and door contact based sensors.
• Bluetooth low energy BLE based prototypes for Intel SoC.