Anupama Mudholkar

Engineering Manager

Bengaluru, Karnataka, India23 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

21+ years in the semiconductor industry.
Expert in system architecture and RTL design.
Proven leadership in global engineering teams.

Stackforce AI infers this person is a Semiconductor Engineering Expert with extensive experience in design and development.

Contact

Skills

Core Skills

ArchitectureDesignTestchip DevelopmentAutomationDevelopment

Other Skills

Functional VerificationFormal VerificationSOC IntegrationMentoringSpecificationSynthesisLECMBISTATPGRTL codingGate Level simulationSoCASICVerilogVLSI

About

Entrepreneur, Technologist, 21+ years of core Technical Semiconductor Industry Experience. + Expert on system Architecture, Micro-architecture, RTL Design, Verification. + Experience in working with global multi site engineering teams. + Excellent written, verbal and presentation, communication ,Interpersonal and leadership skills. + Expertise in understanding customer requirements and translating into successful product. + Knowledge and exposure to complete IC design flow from requirements to silicon.

Experience

23 yrs 10 mos

Total Experience

2 yrs 11 mos

Average Tenure

8 yrs 6 mos

Current Experience

Intel corporation

2 roles

Engineering Manager

Promoted

Jul 2020 – Present · 5 yrs 10 mos

Senior Member Of Technical Staff

Oct 2017 – Jun 2020 · 2 yrs 8 mos

Collabrill | zerobench

Co Founder

May 2016 – Oct 2017 · 1 yr 5 mos · Bangalore

Intel corporation

Member of Technical Staff

Mar 2011 – Mar 2015 · 4 yrs · Bengaluru Area, India

Architecture, Design and Development of Digital HW Wireless IPs . As a Technical Project lead was responsible for end-to-end solutions. Collecting the requirments, Design, Functional Verfication, Formal verifcatin, SOC Integration , post silicon deug support. Interactions with Firmware team to get the final product working. Coming up with new methodology to establish IP Development flow.
Mentoring/ Training new Team members.

ArchitectureDesignDevelopmentFunctional VerificationFormal VerificationSOC Integration+1

Infineon technologies

Senior Design Engineer

Sep 2009 – Feb 2011 · 1 yr 5 mos · Bengaluru Area, India

Testchip Development : Responsible for complete execution of testchips with different technologies (28nm, 40nm, 65nm) . Full ownership of Frontend activities. From Specification to synthesis, LEC.,MBIST, ATPG , Tap controller activities.
Worked and coordinated many Automation projects to get rid of monotonous and time consuming activities. Coordinating between different stack holders.
Mentoring/ Training new Team members.

Testchip DevelopmentSpecificationSynthesisLECMBISTATPG+1

Conexant

Lead Design Engineer

Jun 2006 – May 2008 · 1 yr 11 mos · Bengaluru Area, India

Design and Development of MoCA PHY.
As a Lead Designer was responsible for ,
Understanding of the MOCA Specification , Architecture, design and RTL coding for complex MOCA link controller module. Single point contact for co-ordination activity between Firmware and HW integration.Gate Level simulation with SDF. Responsible for co-ordination between backend and frontend Activities.

DesignDevelopmentRTL codingGate Level simulation