Mar 2022 – Jan 2026 · 3 yrs 10 mos · Noida, Uttar Pradesh, India

Dec 2015 – Mar 2022 · 6 yrs 3 mos · Noida Area, India

Apr 2014 – Dec 2015 · 1 yr 8 mos · Bengaluru Area, India

• PLLs, High Speed DACs

Jan 2009 – Apr 2014 · 5 yrs 3 mos · Hillsboro, OR

• High Speed Serial IO, Tx,Rx,Clocking

Aug 2007 – Dec 2008 · 1 yr 4 mos · University of Florida, FL

• A Low power, digital PLL based, adaptive body biasing circuit enabling ultra-low voltage sub-threshold operation of digital circuits across all process corners. Successfully fabricated and tested a chip in UMC-130nm.
• Design of Standard CMOS Logic process compatible (Single Poly) Flash memory cells, with peripheral read/write/error checking circuitry and a high voltage charge pump, for RFID applications. Successfully fabricated and tested a chip in UMC-130nm.
• Design of basic infrastructure such as IO-PADS, Decoupling cells, Extended Drain Devices, IO Buffers and Power Distribution Network for TI-65nm Process.
• Design of a 1K-bit, Low Voltage SRAM along with the peripheral read write circuitry in the MITLL-3D SOI process.

May 2005 – Jul 2006 · 1 yr 2 mos · Bengaluru Area, India

• Emulator development for Intel Xscale architecture based Network Processors.

Jan 2005 – Apr 2005 · 3 mos · Noida Area, India

• Device driver development for set top boxes.