Divyansh Chauhan

Software Engineer

New Delhi, Delhi, India4 yrs 9 mos experience

Most Likely To Switch

Key Highlights

Expertise in Bare Metal CPU validation concepts.
Proven track record in ARM and Custom NUVIA CPU-based SoCs.
Experience in managing complex validation projects.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in ARM architecture and CPU validation.

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Skills

Core Skills

Cpu ValidationArm Architecture

Other Skills

C++Test ProceduresDebuggersCPython (Programming Language)Machine LearningData StructuresSoftwareComputer ScienceAnalytical SkillsData ScienceComputer EngineeringCritical ThinkingCreative Problem SolvingProblem Solving

About

Currently working as a Pre and post-silicon Bare Metal Validation Engineer with a total experience close to 2.5 years in Qualcomm. Proven track record of driving and delivering on ARM and Custom NUVIA CPU-based complex SoCs. CPU validation engineer with responsibility for project execution and all quality milestone deliverable. Expertise in Bare Metal CPU validation concepts and exposing HW Bugs.

Experience

4 yrs 9 mos

Total Experience

1 yr 7 mos

Average Tenure

1 yr 8 mos

Current Experience

Qualcomm

Senior Engineer

Aug 2024 – Present · 1 yr 8 mos

Amd

Senior Silicon Design Engineer

Mar 2024 – Aug 2024 · 5 mos

Worked on AMD Zen CPUs, validating issues across silicon, firmware/BIOS.
Development and running x86 content to exercise new features and reproduce complex bugs in silicon.
Devised validation strategy from pre-silicon through customer adoption working across architecture, silicon
design, firmware, validation, and debug teams.

Qualcomm

2 roles

Engineer

Promoted

Dec 2022 – Feb 2024 · 1 yr 2 mos

Currently working on in-house designed ARM-based Custom CPUs by Qualcomm, validating architectural and
micro architectural features on pre-post silicon platforms for MSM and compute projects.
Developing end-to-end directed and random test cases for feature validation of CPU Subsystem.
Developed randomized stimulus from scratch targeting CPU features like page table, MMU, caches, coherency,
CPU Low Power Modes, DFVS, ARM GIC, Watch Dog, Arch timers.
Worked on multiple gating HW bugs, recreation on Silicon the platforms reported by customers, SW teams,
resolving the issues and providing the workarounds to unblock the customers.
Managed Directed and Random regressions on volume devices and their debugs with a team of 10 validation
engineers.
Experience with pre (emulators, simulators, FPGA based platforms)/post-silicon BareMetal validation of
ARM/NUVIA (custom CPU) based sub-system.
Worked with CPU coherency, caches, timers, Generic Interrupt Controller and several other ARM features and
debugged many design bugs around it.
Developed an infrastructure that helps to run executable binaries generated from the RIT in pre/post-silicon
environment, which helped to find and debug many critical design bugs.
Developed an python based automation framework that is able to run the different test cases under regression.