Apr 2012 – Sep 2018 · 6 yrs 5 mos · Bengaluru, Karnataka, India

• Designed and developed DNN inference library for Samsung Neural network Processor (SNP)
• Designed and developed Samsung Convolutional Deep Neural Network Model Visualizer using Eclipse RCP
• Designed and developed Profiler for Samsung Reconfigurable Processor (SRP)
• Developed Integrated Development Environment (IDE) for SRP using Eclipse CDT
• Ported LLDB Debugger for SRP

Jul 2011 – Apr 2012 · 9 mos · Bengaluru, Karnataka, India

• • Ported GDB for Samsung Reconfigurable Processors (SRP)

Apr 2010 – Jul 2011 · 1 yr 3 mos · Greater Chennai Area

• Maintenance of existing GNU tool chain for a RISC processor (ABACUS)
• Added support for a new architecture in GNU tool chain
• Extensive testing of ported GNU tool chains

Oct 2007 – Mar 2010 · 2 yrs 5 mos

• GCC Prototype Compiler for a VLIW DSP:
• Enabled auto-vectorization in GCC for porting it to 16bit VLIW DSP architecture.
• Framed GCC training materials. Framed theoretical and practical exercises for trainees.
• Trained members on GCC compiler basics and on GCC porting. The members were able to get into porting work within the training period of 4 calendar months.
• Assembly Translator for CISC architectures:
• Contributed to the overall design of assembly translator.
• Implemented "target translator" (programming language C++) for translating the assembly of two different CISC architectures to the assembly of a new CISC architecture. This was a prototype implementation. Based on the prototype, the customer awarded the project.

May 2005 – Sep 2007 · 2 yrs 4 mos

• DSP-C Cross Compiler for iCore3:
• Worked in backend development (programming language C) and maintenance of 'DSP-C' compiler (for 16 bit DSP).
• Implemented pipeline hazards optimization for 16 bit DSP compiler. Customer changed the pipeline hazards specification after the implementation. But the change was incorporated into the implementation without any design change. Such was the design made initially.
• Contributed to the implementation of Instruction Level Parallelism (ILP)
• Implemented the interface between Instruction Level Parallelism (ILP) and Pipeline hazards optimization.
• Implemented the Multiplication and Accumulation (MAC) module.

Jul 2004 – Apr 2005 · 9 mos

• C Cross Compiler for U8 core:
• Worked in black box testing of 'C' compiler for 8 bit RISC microcontroller.
• Wrote test specifications for data segment pragma and optimization pragma.
• Derived minimized decision tables for the test specification.
• Wrote black box tests based on the minimized decision tables.
• Used AQVS (acme quality validation system) for regression testing.
• Validated assembly differences - regression output validation.
• Ran tests using simulator and emulator. Verified output logs.
• Reviewed design specification of modules under development.