Keyurkumar A Mistry

Director of Engineering

Bengaluru, Karnataka, India19 yrs 6 mos experience
Highly Stable

Key Highlights

  • Led 15+ SoC projects from conception to execution.
  • Expert in complex SoC design and delivery.
  • Proven leadership in managing large engineering teams.
Stackforce AI infers this person is a Semiconductor Engineering Leader with expertise in complex SoC design and development.

Contact

Skills

Core Skills

Technical Staff ManagementManaging Technical PersonnelSoc Design ArchitectureStrategic LeadershipD-phy Digital Ip DevelopmentHigh-speed Serial Communication DesignRtl Design

Other Skills

Power managementSecurityDFDUPFMIPI standards5G mobile networkMicroarchitectureSynthesisSimulationsPower Management Logic DesignPost-Si Debug Support:Hands-on Technical LeadershipProject StaffingInterconnect ProtocolsMicrocontroller SoC Development

About

๐Ÿš€ Director of Engineering | 18+ Years in Semiconductor Industry ๐Ÿ’ก With a wealth of experience in leading teams to develop cutting-edge microcontrollers, mobile multimedia processors, and networking server chips, I have a proven track record of delivering high-quality silicon on time. Successfully led 15+ SoC projects from conception to execution. ๐ŸŒŸ Expertise of MIPI D-Phy, PCIe, CXL, UCIe D2D, LPDDR5 and PHY protocol, interface and integration Currently managing a team of 30+ engineers in RTL SoC digital design for complex networking server SoCs. Key responsibilities include: Leading design tasks: Clocking, Reset, Power Management, DFD, Security, UPF, and RTL Quality Checks. Collaborating with microarchitecture teams to ensure timely and high-quality RTL delivery. ๐Ÿ› ๏ธ Coordinating with cross-functional teams: Verification, Emulation, Timing, PNR, and Firmware for smooth RTL releases and resolving interdependencies. Past contributions include: D-PHY Digital IP Development for mobile devices ๐Ÿ“ฑ 5G Mobile Network Controller SoCs ๐ŸŒ High-Performance ARM-Based Subsystems ๐Ÿ”ง Expertise in TI C2000 Microcontroller SoCs and Complex Multimedia SoCs like OMAP3430/OMAP3630. Proficient in RTL Design, Static Timing Analysis (STA), Power Management, and Complex System Integration. Adept at driving EDA Vendor Solutions, providing technical guidance, and collaborating with top management to define project schedules, mitigate risks, and overcome execution challenges. ๐Ÿ†

Experience

19 yrs 6 mos
Total Experience
4 yrs 6 mos
Average Tenure
1 yr 6 mos
Current Experience

Amd

Principal Member of Technical Staff

Nov 2024 โ€“ Present ยท 1 yr 6 mos ยท Bengaluru, Karnataka, India ยท On-site

Technical Staff ManagementManaging Technical Personnel

Intel corporation

3 roles

Director of Engineering

Promoted

Apr 2024 โ€“ Nov 2024 ยท 7 mos

  • Leading Complex SoC Design & Delivery
  • Spearheading RTL design for complex Networking server SoCs with a team of 28+ engineers. Driving design tasks including clocking, reset, power management, fabrics, DFD, security, UPF, and RTL quality checks. Collaborating closely with the microarchitecture team to develop RTL designs from specifications and ensuring high-quality delivery on time. ๐ŸŒŸ
  • Cross-Functional Leadership & Collaboration
  • Coordinating with Verification, Emulation, Timing, PNR, and Firmware teams to resolve interdependencies. Driving EDA vendors to enhance solutions for complex architectures. Providing strategic planning, tracking, and technical guidance to engineers.
  • Strategic Planning & Execution
  • Working with top-level management to define schedules, set priorities, mitigate risks, and address execution challenges. Serving as Bug Board chairperson for functional bug disposition post-RTL freeze.
  • Key Strengths:
  • Proven leadership in managing large teams and delivering high-quality RTL designs
  • Expertise in complex SoC design, including clocking, power management, and security
  • Strong collaboration and communication skills, with extensive experience across cross-functional teams and top management
  • Technical expertise in RTL design with a focus on quality and innovation
Strategic LeadershipSoC Design Architecture

Senior Engineering Manager

Promoted

Nov 2019 โ€“ Mar 2024 ยท 4 yrs 4 mos

Technical Team Lead

Nov 2018 โ€“ Oct 2019 ยท 11 mos

Infineon technologies

Staff Engineer

Nov 2015 โ€“ Oct 2018 ยท 2 yrs 11 mos ยท Villach Austria

  • Designed cost-effective D-PHY IP for mobile devices, adhering to MIPI standards for optimal performance. Led the design and integration of digital components in 5G mobile network controller SoC, including microarchitecture, synthesis, and simulations for advanced 5G solutions.
D-PHY Digital IP DevelopmentHigh-Speed Serial Communication Design

Mediatek

Staff Engineer

May 2014 โ€“ Oct 2015 ยท 1 yr 5 mos ยท Bangalore India

  • Led a team of 3 engineers in developing a 64-bit ARM-based subsystem for wireless tech. Delivered microarchitecture specs, integrated ARM RTL with CPU subsystems, and handled RTL tag releases. Verified power management, performed gate-level simulations, and supported silicon validation.
RTL DesignPower Management Logic Design

Texas instruments india pvt ltd

Senior ASIC Design Engineer

Jun 2006 โ€“ Apr 2014 ยท 7 yrs 10 mos ยท Bangalore India

  • Developed TI C2000 32-bit microcontrollers for various applications and contributed to OMAP3430/OMAP3630 SoCs with 20M+ gates.
  • Integrated AHB/APB protocols, managed power techniques, and implemented IO muxing for 450 PADs. Created analog IP wrappers, GPIO, and DAC RTL.
RTL DesignPost-Si Debug Support:

Education

Birla Institute of Technology and Science, Pilani

Master's degree

Jan 2003 โ€“ Jan 2005

Birla Vishvkarma Mahavidhyala

Bachelor's degree โ€” Electronics Engineering

Jan 1997 โ€“ Jan 2000

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