Aug 2021 – Jun 2024 · 2 yrs 10 mos · San Jose, California, United States

Jan 2020 – Jul 2021 · 1 yr 6 mos · San Jose, California, United States

Sep 2019 – Dec 2019 · 3 mos · San Jose, California, United States

May 2019 – Sep 2019 · 4 mos · San Francisco Bay Area

• Given a routed clock tree, the buffer library, and the required delay increment value from driver to sink at various nodes in the tree, the project was aimed to develop an algorithm that would recognize if it is possible to increase the delay by the given amount and if yes, then estimate the number of buffers and their locations between the driver and sink to achieve the delay increase in the net as close to the given amount as possible.
• Generated the dataset by parsing the Statistical Timing Analysis (STA) report generated by Cadence Innovus to get the cell and net specifications in the clock tree, e.g. input slew, output slew, cell delay, net delay, etc. and performed statistical modelling to estimate the location and types of buffers that would give the required delay in a particular net under the constraint that the slew at the sink node should not get affected.

Jan 2018 – Jun 2018 · 5 mos · Bryan/College Station, Texas Area

• The project mainly focuses on collecting battery data for different missions and then learning the profiles. The context-sensitive, low battery knowledge allows the UMV to be able to compare remaining battery power with the projected use requirements to complete the proposed mission. The project explicitly represents different missions and the associated time and effort profiles, and uses machine learning, to associate battery use profiles for each of the established missions.

Aug 2017 – Dec 2019 · 2 yrs 4 mos · Bryan/College Station, Texas Area

Apr 2016 – Jul 2016 · 3 mos · Roorkee, India

• I did my undergrad in Electrical Engineering (specialization - VLSI circuits), and as a part of that I did research intern in circuit design field
• Primarily involved in designing the buffer circuit with reduced power dissipation under the circuit delay constraints
• Implemented high-performance logic style: Dynamic Current Mode Logic (DyCML) across various configurations and compared their performances
• Studied the effects of parasitic capacitances on power dissipation and developed the layout for DyCML latch in 180nm SCL technology using cadence