Rajeev Setty Mogalapalli — Software Engineer
Led PCIe Gen6/7, NPU and GPIO IP/Subsystem teams for various products. Total experience of ~14years in Intel, Qualcomm and Broadcom handling various Design & Architecture tasks and worked specifically on High Speed Serial IO IPs (PCIe, QPI) and also NPU (Neural Processing Unit) + AI/Computer Vision related IPs/Subsystem. Owned RTL design of many critical features for multiple 3/4/5/7nm products and also is an expert on various RTL flows/tools. Drove Component Debug and HVM activities for these blocks and had good experience in Post Silicon debug. Expert in low power RTL design and UPF coding. Showcased excellent Leadership skills and tremendous stakeholder management skills.
Stackforce AI infers this person is a highly skilled engineer in VLSI and semiconductor design.
Location: Bengaluru, Karnataka, India
Experience: 16 yrs 2 mos
Skills
- Rtl Design
- High Speed Serial Io Ips
Career Highlights
- 14 years of experience in leading design and architecture teams.
- Expert in low power RTL design and high-speed serial IO IPs.
- Proven leadership and stakeholder management skills.
Work Experience
Broadcom Inc.
Principal Engineer (4 yrs)
Qualcomm
Staff Engineer (4 yrs 4 mos)
Intel Corporation
RTL Design Engineer (5 yrs 7 mos)
Intel India Technology Pvt Ltd
Intern (6 mos)
GSS America
Intern (2 mos)
EEE and ECE Association, BITS-Pilani Hyderabad Campus
Treasurer (1 yr)
Saint Marys High School
President, Students' Union (9 mos)
Education
M.Tech - MicroElectronics (WILP) at Birla Institute of Technology and Science, Pilani
Bacherlor of Engineering at Birla Institute of Technology and Science, Pilani
Intermediate at Sri Chaitanya Junior College
SSC at Saint Marys High School, Yellamanchili, Vishakapatnam
