Jun 2016 – Apr 2018 · 1 yr 10 mos · Bengaluru, Karnataka, India

• Head of Program Management & Operations - Bangalore Design Center
• Responsible for program management of all programs executed at the center
• Responsible for engineering operations
• Responsible for Process & Methodology, logistics, labs and quality at site

Oct 2011 – May 2015 · 3 yrs 7 mos · Bangalore, India

• Head of IP Engineering - Process & Circuit Technology India Design organization with 160+ people
• Responsible for 5 vertical Analog/ Mixed Signal (AMS) & Foundation IP design groups – SOC circuits/Clock design, IO, Memory compilers, Std cell/ PDK and Test chip in technology 20nm and below
• Responsible for 4 horizontal design groups – AMS/IP verification, Custom Layout, Physical design, CAD
• Responsible for people management/development, career path, performance appraisals and budget management
• Built 4 new teams – Test chip, IO, Memory compilers, Physical design
• Team size doubled in 2 years
• Building Centre of Excellence (CoE) in Analog Mixed Signal IP verification, Custom Layout, Physical design & Testchip

Aug 2010 – Sep 2011 · 1 yr 1 mo

• Initiated New End Equipment (NEE) business group in India to develop new business opportunities using TI DSP technology and provide complete system solution to customers in Asia Pacific Region.
• Focusing on Advanced displays and Smart Energy and Power businesses and responsible for Product Management; Business Development, Market Segmentation, Eco System development, and Customer Management

Sep 2008 – Aug 2010 · 1 yr 11 mos

• Head of DSP system India Design organization with around 100 people
• Part of Business Unit (BU) leadership team responsible for $500M business; responsible for driving strategic planning for new products identification/definition and their execution.
• Responsible for all designs/products for application processors and floating point BU and ARM MPU BU from product definition to tapeout.
• Responsible for people management, their development, career path, performance appraisals and budget management
• Led first technology driver (40nm) design; Netra, Integra family; C6A816x; industry’s fastest floating point DSP (1.5GHz) and Cortex A8 (1.5GHz) with extreme integration of peripherals for video surveillance and video conference markets

May 2006 – Sep 2008 · 2 yrs 4 mos

• Responsible for project management of multiple SOCs in communications/ wireless infrastructure, video security/surveillance applications and audio from specifications to tapeout·
• The infrastructure product family includes TMS320C6454/55 and TMS320TCI6482. This is first 1GHz fixed point DSP core C64+ from TI in 90nm along with many peripherals like PCI 66MHz, DDR2 532 MHz, Gigabit Ethernet MAC
• The video security/ surveillance product family includes TM320DM647/648 and TMS320C5451/52

Mar 2004 – May 2006 · 2 yrs 2 mos

• Responsible for project management of SOCs in performance audio and broad catalog market from specifications to tapeout.
• The product family includes DA710/708/70Y for PA and TMS320C6727/26/22 for broad catalog market.
• o Best Audio DSP of 2005 by In-Stat\
• o The Hot 100 products of 2005 – processors category by EDN

Mar 2000 – Feb 2004 · 3 yrs 11 mos

• Project Management, group leader and senior member for projects with gate count over 3+M, frequencies up to 250MHz in technologies 0.13u
• Domain - Networking, Interworking and Access Integrated circuits from concept to tapeout

Oct 1998 – Feb 2000 · 1 yr 4 mos · Singapore

• Responsible for verification and synthesis tools and design services to customers in South-East Asia.
• Responsible for product demos, bench-marking with competition tools, technical presentations, training and design services
• Development of design flows from System Level design to Place and Route using system level, simulation, synthesis and P&R tools for customers

Jun 1996 – Sep 1998 · 2 yrs 3 mos · Singapore

• Responsible for development of integrated circuits, system board designs, applications. The job scope involved from graphics IC design to system prototype and interface to the engineering department till mass production
• Responsible for development of product lines - Graphics Blaster 3D Series – PCI based graphics card and Video Blaster IE500 Series – PCI based video capture card

Apr 1993 – May 1996 · 3 yrs 1 mo

• - Responsible for development of board designs, systems, applications, firmware and software using DSPs/ Microcontrollers/ Microprocessors