S

Saurabh Gupta

DevOps Engineer

Bengaluru, Karnataka, India16 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in HPC and AI/ML workload performance.
  • Published research on memory system design and resilience challenges.
  • Strong background in CPU microarchitecture and computer systems.
Stackforce AI infers this person is a high-performance computing architect with expertise in resilience and optimization.

Contact

LinkedIn

Skills

Other Skills

MatlabSimulationsC++CAlgorithmsLaTeXData AnalysisProgrammingPythonLinuxStatisticsResearchRSignal ProcessingMicrosoft Office

About

*At AMD: Server Performance Architect with focus on HPC and AI/ML workloads performance. *At IITK/NCSU/ORNL/Intel-Labs: Research on CPU Microarchitecture and Computer Systems. Extensive published work on Locality Analysis, Memory System Design, High-performance computing (HPC), and Resilience challenges at large-scale (https://sites.google.com/site/saurabg/)

Experience

16 yrs 6 mos
Total Experience
3 yrs 4 mos
Average Tenure
5 yrs 3 mos
Current Experience

Amd

2 roles

Principal Member of Technical Staff

Promoted

Jul 2025 – Present · 10 mos

Senior Member of Technical Staff

Jan 2021 – Jun 2025 · 4 yrs 5 mos

Intel labs

Research Scientist at Process Architecture Research Lab

Jul 2016 – Jan 2021 · 4 yrs 6 mos · Bengaluru Area, India

  • CPU Front-end Architecture

Oak ridge national laboratory

Post-doctoral Research Associate

Jan 2014 – Jun 2016 · 2 yrs 5 mos · Oak Ridge, TN

  • Fault-tolerance and Resilience for HPC Systems, Multicore systems research for HPC, I/O behavior and optimization

Orau

ASTRO Program Participant

May 2013 – Aug 2013 · 3 mos · Oak Ridge

  • Technology Integration Group: Energy-efficient and Adaptive Checkpointing Strategies for HPC

Intel corporation

Graduate Summer Intern

Jun 2012 – Aug 2012 · 2 mos · Santa Clara

  • Server Development Group: Solving Performance Bottlenecks in I/O subsystem for server CPUs

North carolina state university

2 roles

Research Assistant

Promoted

May 2010 – Dec 2013 · 3 yrs 7 mos

  • Intel URO Swiss Army Program: Achieving Performance and Power Efficiency for Single-thread Applications

Graduate Teaching Assistant

Aug 2009 – May 2010 · 9 mos

  • Office hours (clarify concepts, homework questions, help with debugging circuits), grading homework assignments, and evaluate circuit projects

Ibm

Summer Intern STG

May 2007 – Jul 2007 · 2 mos · Bangalore

  • Instruction Execution Driven Simulator for IBM PowerPC Architecture

Education

North Carolina State University

Doctor of Philosophy (PhD) — Computer Engineering

Jan 2009 – Jan 2014

Indian Institute of Technology, Kanpur

B.Tech. - M.Tech. Dual Degree — Electrical Engineering

Jan 2004 – Jan 2009

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