Nov 2020 – Sep 2022 · 1 yr 10 mos

• Currently, I am working in the ESXi hypervisor performance team specializing in the CPU and Memory performance of the kernel. I maintain and develop a couple of performance monitoring tools for ESXi.

Jul 2016 – Oct 2020 · 4 yrs 3 mos

• Currently, I am working in the ESXi hypervisor performance team specializing in the CPU and Memory performance of the kernel. I maintain and develop a couple of performance monitoring tools for ESXi.

Oct 2014 – Jul 2016 · 1 yr 9 mos

• I worked in the ESXi hypervisor performance team specializing in the CPU and Memory performance of the kernel. I maintain and develop a couple of performance monitoring tools for ESXi.

Jun 2013 – Aug 2013 · 2 mos · Palo Alto, CA

• I worked in the ESXi performance team specifically on memory management. I developed a fast compressibility checker which can be used to check memory pages for compressibility. Using this checker, I developed a content based swap candidate selection algorithm in ESXi memory scheduler. My algorithm improved the swapping performance of ESXi hypervisor significantly.

Jan 2011 – Aug 2011 · 7 mos · Champaign, IL

• I worked in the Thread-checker team. I developed a distributed thread checking tool which enables the threading analysis (data race and deadlock detection) on various platforms ranging from embedded systems to data centers. I received Division Recognition Award for this work.

Aug 2008 – Sep 2014 · 6 yrs 1 mo · State College, Pennsylvania Area

• A Study of Parallelism-Locality Tradeoffs Across Memory Heirarchy (Advisor: Dr. Mahmut Kandemir)
• In modern Chip Multi Processors, both memory and on-chip network are crucial resources. In my PhD, I developed techniques to mitigate bottlenecks in such systems and increase efficiency of these critical resources. I developed a novel memory-side prefetching scheme. I combined my memory-side prefetching with existing core-side prefetching to build a cooperative prefetching scheme which is better than either of them. I addressed the NUMA issue of these modern processors by developing an efficient memory data migration scheme which incurs minimum overhead.
• I worked in the development of a simulation platform (GEMDROID: http://huz123.github.io/gemdroid.htm) for full system modeling of an SOC based mobile device. Using this platform, we designed new hardware modules and scheduling algorithms for SOCs.
• I also worked on the automatic parallelization problem. I developed a method to combine programmer hints, compiler analysis and runtime information in-order to automatically parallelize programs involving pointers and dynamic data structures.