Feb 2012 – Nov 2018 · 6 yrs 9 mos · Hillsboro

• Staff Research Scientist, Circuits Research Lab, Intel Corporation: High performance and energy efficient accelerator design and prototyping for hardware Security, Data Compression and On-die switch fabrics (10+ years experience). Led architecture definition and silicon prototyping of next generation IA accelerators, new instruction hardware and ASICs in sub 10nm process technologies.

Apr 2011 – Aug 2011 · 4 mos · Hillsboro

• Proposed novel circuit techniques to improve latency and energy efficiency of on chip routers and improve scalability using source synchronous and priority based communication circuits. My work resulted in two invention disclosures.

Aug 2007 – Dec 2011 · 4 yrs 4 mos · Ann Arbor

• My research on swizzle switches and high radix on-die permutation networks resulted in the development of 4 test prototypes, 7 patent filings in the US, 5 in the UK, and 5 in Japan apart from 11 publications 6 of which featured in ISSCC and VLSI Symposium. 2 of my projects have won student design contest awards (one of them as the lead designer). As a member of MICL (Michigan Integrated Circuits Lab), I contributed to many successful funding expeditions from NSF, DARPA, Intel Corporation, Quallcom, ARM Ltd. etc. I was leading the research on on-die interconnect fabrics from Umich and drove joint collaboration with researchers from ARM Ltd. in a 5 year funded research program.

Apr 2006 – Jul 2006 · 3 mos · Greater Munich Metropolitan Area

• Working with the Chip-Card design group, I designed the testing board and set up the testing environment in Lab-View for the first lot of test-chips of a novel floating gate based Flash memory cell. My set up could uncover a flaw in the design layout that was rectified in the successive lot of flash cells.