Jayesh Gaur

CTO

Bengaluru, Karnataka, India21 yrs 8 mos experience

Highly Stable

Key Highlights

Led core architecture for next generation IBM POWER Cores.
Filed 60+ US patents in computer architecture.
Best paper awards at top architecture conferences.

Stackforce AI infers this person is a Semiconductor Architect with extensive experience in CPU architecture and performance optimization.

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Skills

Core Skills

Computer Architecture

Other Skills

MicroprocessorsC (Programming Language)ASICSoCRTL designVerilogFunctional VerificationPerlCircuit DesignFormal VerificationMatlabSpecmanMicroarchitectureShell ScriptingVLSI

About

Expert computer architect leading the Core architecture of next generation IBM POWER Cores. As core lead, I am responsible for the core IP from concept to tape out and beyond. Prior to this role I was a Principal Engineer at Intel working on core architecture enhancements to improve the per core performance and performance/Watt of Intel CPUs. I had also worked on the Uncore architecture of the Skylake family of Intel processors, building architectures for the Last Level Cache and Ring interconnect. I have filed for 60+ US patents in computer architecture and have widely published in top architecture conferences. I received best paper awards at ISCA 2024 and HPCA 2017 and a best paper runners up award at HPCA 2021. I was admitted to the hall of fame of the ISCA conference. I studied at the University of Michigan Ann Arbor and at IIT Kanpur.

Experience

21 yrs 8 mos

Total Experience

6 yrs 9 mos

Average Tenure

1 yr 3 mos

Current Experience

Ibm

Chief Architect of Power Core

Jan 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

Working on next generation IBM Power Cores.

Computer ArchitectureMicroprocessors

Intel labs

2 roles

Principal Engineer, CPU Architect

Mar 2021 – Jan 2025 · 3 yrs 10 mos · On-site

Leading path finding of next generation CPU architectures for Intel cores.

Computer ArchitectureMicroprocessors

CPU Architect and Manager

Jan 2016 – Mar 2021 · 5 yrs 2 mos · On-site

Focus on next generation, high performance, out of order cores. Looked at various power performance solutions in out of order execution, high bandwidth instruction fetch and branch predictors, predication solutions for H2P branches, data speculation (value prediction), disambiguating, memory prefetching/compression etc.

Intel corporation

CPU Architect and Manager

Aug 2009 – Dec 2015 · 6 yrs 4 mos

I worked as a CPU architect with focus primarily in the areas of Shared Caches and Memory Subsystems for next generation Intel System on Chips.
Efficient Cache management for CPU/GPU, Performance/Power modeling and analysis, Large cache architectures, Multi-Level memories