Saurabh Rajput

Co-Founder

Delhi, India10 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Co-founded two successful quantitative trading firms.
Expert in algorithmic trading and mathematical modeling.
Developed low latency trading platforms for major exchanges.

Stackforce AI infers this person is a Fintech expert specializing in algorithmic trading and quantitative analysis.

Contact

Skills

Core Skills

Algorithmic TradingMathematical ModelingHigh Performance ComputingMachine LearningStatistical Signal Processing

Other Skills

MatlabExcelData AnalysisPythonC++AlgorithmsSignal Processing

About

Working in the field of quantitative trading domain with the focus on generating alpha through mathematical modelling, market microstructure inefficiencies exploitation and scaling through technology.

Experience

10 yrs 3 mos

Total Experience

4 yrs 11 mos

Average Tenure

8 yrs 11 mos

Current Experience

Alpha equations pte. ltd

Co-Founder

Sep 2021 – Present · 4 yrs 8 mos · Singapore · Hybrid

Delivering lowest latencies and deploying state of the art trading strategies to provide pricing efficiencies across global financial markets.

MatlabExcelData AnalysisMathematical ModelingPythonC+++1

Rtheta

Co-Founder

Jun 2017 – Present · 8 yrs 11 mos · Gurugram, Haryana, India

Cofounded a quantitative trading firm with a focus on high frequency trading.Rtheta has developed a low latency trading platform which is live in National Stock Exchange. Rtheta's expertise lies in algorithmic trading, high performance computing and mathematical modelling.
Key Skills: Algorithms, High Performance Computing, Machine Learning.

AlgorithmsHigh Performance ComputingMachine LearningAlgorithmic Trading

Marketopper

Quantitative Analyst

Nov 2015 – Mar 2017 · 1 yr 4 mos · Gurgaon

Worked on research projects with India's top academics on Machine Learning, Statistical Signal Processing and Evolutionary Algorithms and designed trading products based on the same. These products were successfully deployed as trading products in the National Stock Exchange
Key Activities: Ideation, POC modelling, and Implementation.

Machine LearningStatistical Signal Processing

Nvidia

Engineer, ASIC Design

Aug 2011 – Oct 2011 · 2 mos · Bangalore

Was Responsible for Developing and Maintaining the Verification Infrastructure for Verilog based Chip Design in the Mobile R&D team at NVidia.

Manthan semiconductors

Research Intern

May 2009 – Jul 2009 · 2 mos · Bangalore

Designed Transceiver Model in Matlab operating at 5 Gigahertz frequency in accordance with then recently released USB 3.0 standard.
Identified and implemented "Mueller and Muller" clock recovery method as a solution to high speed symbol synchronization problem.