Dec 2024 – Apr 2025 · 4 mos · Vancouver, British Columbia, Canada · Hybrid

• Admin Foundations Team
• Converted internal projection models to industry-standard GraphQL interfaces enabling fragmentization and schema consistency
• Refactored Admin Console loading processes and streamlined data retrieval to boost performance and maintainability
• Built a few proofs of concept for an Admin Console revamp leveraging main app framework enhancements

Oct 2022 – Nov 2024 · 2 yrs 1 mo

• As part of a dynamic and highly collaborative team at Amazon Macie, I've been dedicated to addressing our customers' critical data security requirements. My journey at Amazon Macie began with an initiative to optimize cost-efficiency by reducing ECS-related expenses, resulting in significant savings of 20-30% through the elimination of duplicate classification tasks.
• In more recent endeavors, I've played a pivotal role in advancing Macie's capabilities to proactively identify and report sensitive information, such as Google Cloud API keys, Stripe API keys, and confidential identification numbers, including Aadhaar, PAN, and driver's license data for India. These enhancements align with Macie's mission to provide state-of-the-art data protection and compliance solutions.
• For more details about Macie's powerful features, please visit: https://docs.aws.amazon.com/macie/latest/user/managed-data-identifiers.html
• Discover how Amazon Macie is revolutionizing data security: https://aws.amazon.com/macie/

Aug 2020 – Oct 2022 · 2 yrs 2 mos

• As part of Visual Search and AR Team, we are responsible for the platform underneath Amazon App's Camera Search, StyleSnap and Augmented Reality features.
• I worked on a project which ensured GDPR and CCPA compliance for Visual Search and Save Your Room services. We automated On Demand Deletion requests from our customers, swiftly deleting diverse customer data, including images and clickstream, all the while maintaining an audit trail and meeting SLA requirements. Apart from the legal challenges, there were a few scalability challenges to be surmounted as well.
• I also contributed to the development of an Image-to-Text Query service that harnessed customer behavioral data to convert product image queries into text queries, delivering tailored results. Collaborating with data scientists, MLOps teams, mobile engineers, and quality assurance engineers, we enhanced the Amazon Lens experience in the Top-8 locales, spanning Hardlines, Consumables, and Media categories. This work resulted in a patent application. Additionally, I conducted multiple data-driven A/B experiments, leveraging my custom-built data pipelines to optimize the customer experience.

Jul 2018 – Aug 2020 · 2 yrs 1 mo

• Backend engineer at Amazon, responsible for sourcing requirements, architecting and implementing a web dashboard to help Lab 126 teams with their day to day work.
• Primary Programming language used: Python

Sep 2015 – Mar 2018 · 2 yrs 6 mos · San Francisco Bay Area

• Implemented the arbitrator used for validating performance of Teralynx, capable of handling 2.4 Tbps line rate traffic.
• First component to achieve 99% code coverage across the board.
• Designed and developed a TestBench implementing OOP principles using C++, enabling software interrupt validation, multicasting and rainy day testing.
• Implemented the automation pipeline using Jenkins, providing a Continuous Integration environment for verification.
• Created a Perl wrapper to process output of regression runs and improved result reporting.

Jan 2014 – Aug 2015 · 1 yr 7 mos · Santa Clara

• As a part of an experienced FPGA team, made enhancements to the UVM based test bench environment for verification of FPGA based Flow Engine capable of handling up to 20 Gbps network traffic.
• Analyzed coverage reports and with inputs from the designer, enhanced the tests to improve the coverage.
• Wrote test cases in System Verilog using UVM libraries for functional coverage of the Flow Engine and filed bugs when the behavior was inconsistent with the specs.
• Completed and added the tests to regression and ran weekly regressions to improve the coverage.

Jul 2012 – Jan 2013 · 6 mos · Durham, NC

• Modified C code to solve the synchronization issue between NIC adaptor and host CPU in one-sided RDMA operations.
• One-sided operations helped scale the number of clients connected to a server by two orders of magnitude and increase throughput by 10x as it offloaded server's CPU load using a lock manager.

Aug 2011 – Dec 2013 · 2 yrs 4 mos · Raleigh-Durham, North Carolina Area

• Internet Protocols (NCSU): Implemented the Go-back-N automatic repeat request (ARQ) scheme on top of UDP, in Java, for Simple File Transfer Protocol, making it a reliable data transfer service. Implemented a client-server architecture in which the client is the sender of the data and server is the receiver. Implemented a probabilistic loss of data at the receiver end and studied the effect of change in loss probability vs the time taken for data transfer.
• Digital ASIC Design (NCSU): Implemented a Hardware Accelerator running Dijkstra's algorithm in Verilog for finding shortest path between a source-destination pair using Modelsim and Synopsys for simulation and synthesis. It led to a total area utilization of 4237 um2 and a clock period of 9 ns.
• Advanced Parallel Computer Architecture (NCSU): Modified Ruby Simulator to evaluate DSI (Dynamic Self Invalidation) scheme in order to reduce coherence overhead in shared-memory multiprocessors systems. For 8-core systems, we observed a saving of 2.41% in application execution time
• Architecture of Parallel Computers (NCSU): Implemented a trace driven simulator using a C++ generic class cache and built MSI, MESI and MOESI coherence protocols on top of it. Statistics such as transitions between different states, cache to cache transfers, invalidations and flushes were recorded with different cache capacity and block sizes. MESI was found to be the best performer w.r.t. minimum off-chip bandwidth usage.
• Computer Architecture (NCSU): Created a generic cache module in C++ which could be used at any level in a memory hierarchy and be configured using different design parameters. The replacement policies implemented were LRU and LFU with dynamic aging. The write policies implemented were write-back and write-through. Using trace driven simulation the impact of cache configuration on Average Access Time (AAT) was studied.

May 2010 – Jun 2011 · 1 yr 1 mo

• Master's Thesis
• Network Intrusion Detection System (NIDS) on an FPGA Using a Hybrid Algorithm
• The objective was to embed NIDS on chip using Network Interface Unit of OpenSPARC in order to increase the throughput in high-speed networks of today.
• Hybrid of Aho-Corasick Algorithm and Exclusion Based Signature Matching Algorithm was created and implemented on Xilinx Virtex II Pro FPGA Board. A tool was also created to update malicious IP address database list which were to be blocked. Speeds of up to 118.022 Mpps was achieved.

Aug 2006 – Jun 2011 · 4 yrs 10 mos

• 1. Morphing, Mosaicing and Object Tracking Aug '10 -Sep '10
• Implemented morphing on image pairs using manually selected feature points. Stitched images together taken from different viewpoints and angles using mosaicing techniques and OpenCV library.
• Performed Motion segmentation on a video using Sequential Labelling Algorithm, motion estimation and gaussian pyramid.
• 2. Amplitude Modulated Signal Transmitter and Receiver for Strain Gauge Mar '07 - Apr '07
• Designed an Amplitude Modulated Signal Transmitter and Receiver to obtain information regarding the strain being delivered to a body and then modulating, transmitting and demodulating the signal using a coil based antenna and a strain gauge.
• Useful in finding strain on bridge like structures and sending the information remotely.

May 2009 – Jul 2009 · 2 mos

• Web 2.0 Technologies and Linux Infrastructure, QAI Global Services (May 2009 - Jul
• Understood the organization's detailed structure and working. Based on that reported on how Web 2.0 technologies could fit and be used in the most optimal way for increasing the market presence.
• Implemented successfully an internal forum, integration of social bookmarking sites on their home page, set the procedure up and running for whitepapers to be shared on their blog and also informative slides being shared on slideshare.net
• Apart from above, I also researched on how Linux could be adopted by the company, to help both in terms of savings (to the tune of Rs. 30 lakhs) and in reaping the benefits of using the world class server technology provided by Ubuntu.

May 2008 – Jul 2008 · 2 mos

• Improvement in Design of ACB and MHT, Controls & Switchgear Ltd.
• Detailed study of Air Circuit Breakers, involving research on Magnetic Hold Trigger (MHT) and Under Voltage Trip Device (UVT) was my prime responsibility.
• Demonstrated how the weaknesses in the original design could be rectified to meet the prescribed BIS standards.
• As a result changes were made which made the design faster, decreased heat loss, prevented problems in tripping at a later stage and reduced cost.