Harsh Garg — Software Engineer
R&D Engineer specializing in chip verification (HAV) and emulation at Mentor Graphics (Siemens EDA). With experience working in high-performance teams/startups, I excel in delivering fast-track projects under critical deadlines. I’m responsible for driving the product development and debugging lifecycle, ensuring efficiency and quality throughout. Technical Skill Set: C++, Linux, GDB
Stackforce AI infers this person is a chip verification and emulation specialist in the semiconductor industry.
Location: New Delhi, Delhi, India
Experience: 2 yrs 10 mos
Career Highlights
- Expert in chip verification and emulation.
- Proven ability to deliver projects under tight deadlines.
- Strong background in high-performance team environments.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Senior Member of Technical Staff (1 yr 5 mos)
Member of Technical Staff (1 yr 5 mos)
Mentor Graphics
Software Intern (3 mos)
Santa Clara University
Research Intern (6 mos)
MediaTek
Summer Intern (1 mo)
FOSSASIA
Open Source Contributor (1 mo)
Qiskit Global Summer School
Research Trainee (2 mos)
Emuron
Software Development Intern (11 mos)
Harvard Project for Asian and International Relations (HPAIR)
Delegate (1 mo)
Education
BTech at Delhi Technological University (Formerly DCE)
