Yogesh Agarwal

Director of Engineering

Bengaluru, Karnataka, India24 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in design implementation of complex SoCs.
Proven leadership in high-performance processor design.
Strong background in low power and high-speed designs.

Stackforce AI infers this person is a semiconductor design expert with extensive experience in SoC and multimedia processor development.

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Skills

Core Skills

Design EngineeringProgram Management

Other Skills

Clock Tree SynthesisPower OptimizationTeam ManagementOptimizationOptimization TechniquesScriptingUnified Power Format (UPF)NegotiationKey MetricsData AnalyticsCorrective ActionsWritten CommunicationStakeholder EngagementStrategic PlanningTeam Building

Experience

24 yrs 3 mos

Total Experience

6 yrs

Average Tenure

9 yrs 3 mos

Current Experience

Samsung electronics

Director

Mar 2017 – Present · 9 yrs 3 mos · Bengaluru, Karnataka, India

Design Implementation of complex SoCs ( Exynos Mobile , Modem , Connectivity , AI , Auto) in deep sub-micron technology at Samsung Semiconductor India R&D ( SSIR )

Clock Tree SynthesisPower OptimizationDesign EngineeringProgram Management

Mediatek

Engineering Manager

May 2014 – Mar 2017 · 2 yrs 10 mos · Bangalore

Design Implementation of high speed and low power CPU and multi-core subsystems at High-Performance Processors Technology Team
End products : Multiple wireless devices by Amazon, Xiaomi, LG, Acer, Meizu, Asus, Le and so on...

Clock Tree SynthesisPower OptimizationDesign EngineeringProgram Management

Texas instruments

Member Group Technical Staff | Principal Lead

Apr 2004 – May 2014 · 10 yrs 1 mo · Greater Bengaluru Area

Lead High performance, Low Power design and implementation of CPUs, GPUs, DSP processors etc. for Multimedia processors for Wireless devices and Automotive SOCs.
End products : Multiple Wireless devices by Nokia, Motorola, Samsung, Google, Blackberry, Amazon, LG, Huawei, Panasonic and so on..

Clock Tree SynthesisPower OptimizationDesign EngineeringProgram Management

Centre for development of advanced computing: c-dac

Member Technical Staff

Feb 2002 – Mar 2004 · 2 yrs 1 mo · Pune Area, India

Hardware Design, architecting and Implementation of Complex Algorithms on hardware. from RTL design to software testing on Re-configurable Computing System to accelerate scientific computing on supercomputers and real-time embedded systems
End Products: RCS system on PARAM supercomputer, astronomy, bioinformatics ..