Manoj Kumar leburu

Product Engineer

Bengaluru, Karnataka, India17 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 15 years of experience in SOC verification.
  • Expert in developing mixed language verification environments.
  • Proficient in low power verification methodologies.
Stackforce AI infers this person is a highly experienced professional in semiconductor verification and design engineering.

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Skills

Core Skills

Processor Design VerificationDigital Hardware Design

Other Skills

System VerilogC++Assertion coding in SVAACPIOVMAXIx86 AssemblyARMDigital ElectronicsPCIe

About

15+ years of experience in verification of SOCs/Processors/Processor-SubSystems/HBM-PHY-IP. Currently I am leading the verification activity for ARM-SubSystems & Some in-house custom IPs. Skills: 1. Developing Mixed language (c/c++/SV) verification environments that are very essential to verify processor cores or processor based subsystems. 2. Building Random Constrained verification environments using methodologies like UVM. 2. Using formal tools like VC-formal to verify complex IPs. 3. Developing utility tools using Perl/Python. 4. Low power verification using MVSIM/MVRC. Domain Expertise: 1. Verification of Processor-Cores(x86/ARM). 2. Verification of Processor based SubSystems/SOCs. 3. Verification of Security SubSystems. 4. Verification of PHY IPs ( HBM and CHIP-to-CHIP). Languages: 1. C/C++ 2. ASM (ARM/X86) 3. Verilog/SystemVerilog. 4. Perl/Python. Protocol Expertise: 1. AMBA protocols (APB/AHB/AXI/ACE). 2. HBM.

Experience

17 yrs 7 mos
Total Experience
3 yrs 6 mos
Average Tenure
10 yrs 9 mos
Current Experience

Broadcom inc.

2 roles

Principal Design Engineer

Promoted

Nov 2018Present · 7 yrs 5 mos

Digital HardWare DesignProcessor Design VerificationSystem VerilogC++

Design Engineer - IC4

Jun 2015Oct 2018 · 3 yrs 4 mos

Samsung electronics

Chief Engineer

Apr 2013Jun 2015 · 2 yrs 2 mos · Bengaluru, Karnataka, India

Amd

Senior Design Engineer

Jul 2011Apr 2013 · 1 yr 9 mos

Chelsio

MTS

Oct 2010Jul 2011 · 9 mos

Nvidia

ASIC Design Engineer

Aug 2008Oct 2010 · 2 yrs 2 mos

Education

Indian Institute of Technology, Madras

Mtech — VLSI Design

Jan 2006Jan 2008

Jawaharlal Nehru Technological University

Btech — Electronics and communications

Jan 2002Jan 2006

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