ANIL KUMAR CHANDRASHEKHAR

CEO

Bengaluru, Karnataka, India14 yrs 7 mos experience
Highly Stable

Key Highlights

  • Over 20 years of experience in VLSI Physical Design.
  • Led teams through complex chip design projects with zero escalations.
  • Expert in Static Timing Analysis and Physical Verification methodologies.
Stackforce AI infers this person is a VLSI Physical Design Engineer with extensive experience in semiconductor design and verification.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

VLSI methodologyResource ManagementClock Tree SynthesisEM and IR Analysis and fixingpython scriptingShell ScriptingPhysical VerificationLow-power DesignProject TrackingCommunicationEmployee TrainingPerl AutomationTcl-TkCritical ThinkingProblem Solving

About

Self motivated with 20+ years of total experience with 16+ years demonstrated experience in VLSI Physical Design Engineering. Passionate about technology and technical problem solving. Seasoned with deep VLSI understanding and profound knowledge of Physical Design Implementation, STA convergence and methodology. Leadership experience in directing the activities of business-groups. Adept at planning, developing strategies and proficient tracking skills. Excellent interpersonal and communication skills. Result-oriented, big picture focus, delegating tasks and vision to succeed. Proficient Progress tracker, Problem-solver, team-maker, and consensus builder.

Experience

14 yrs 7 mos
Total Experience
6 yrs 8 mos
Average Tenure
1 yr 3 mos
Current Experience

Meta platforms ltd

Contract ASIC Physical Design Lead

Mar 2025 – Present · 1 yr 3 mos · Bangalore Urban, Karnataka, India · Hybrid

  • Working as a contractor Physical Design Engineer in Meta, California through Wipro.
  • On 3nm technology.
Physical DesignStatic Timing AnalysisVLSI methodologyResource ManagementClock Tree SynthesisEM and IR Analysis and fixing+17

Meta

Contract ASIC Physical Design Engineer

Sep 2022 – Jun 2025 · 2 yrs 9 mos · United States · Hybrid

  • Presently working as a contractor Physical Design Engineer in Meta, California through Wipro.
  • Working on 5nm technology.
Physical DesignRDL planning and routingStatic Timing AnalysisFloorplanningVLSI methodologyEM and IR Analysis and fixing+7

Intel technologies india

Domain Architect - Physical Design

Sep 2020 – Sep 2022 · 2 yrs · Bengaluru, Karnataka, India · Remote

  • Worked for Intel as Contractor through Wipro.
  • Managed and led team of 25 engineers through Synthesis to Tape-out for 7nm networking chip.
  • Owned PD implementation of 21 blocks. Successfully completed the STA closure. Owned the PV, EMIR, CLP and FEV convergence and delivered successfully with zero escalations and with a client satisfaction score of 5/5. Completed all major and intermediate tasks on time with highest quality.
Physical DesignStatic Timing AnalysisVLSI methodologyResource ManagementClock Tree SynthesisEM and IR Analysis and fixing+17

Lakshsemi

Lead PD engineer

Nov 2017 – Sep 2020 · 2 yrs 10 mos · Bengaluru Area, India

  • Client - Marvell Technologies:
  • Led PD team on PD execution of Octeon-T98 and PaloAlto-FE400.
  • Client - Global Foundries:
  • Led teams in PD execution and STA closure of Juniper-BT and Quest-Summit projects. Owned PD execution of two of the critical and complex NOC blocks. Led the teams through PV analysis, fixing and sign-off.
  • Developed and implemented multiple automations.
  • Client - Qualcomm:
  • Led a team of 4 PD engineers through PD execution in Talos. Led a team of 12 through PV signoff. Played the role of PV consultant for the entire team to minimize the TAT in PV sign off.
Physical DesignStatic Timing AnalysisFloorplanningVLSI methodologyClock Tree SynthesisEM and IR Analysis and fixing+8

Intel corporation

4 roles

ASIC Design Engineer

Jul 2013 – Sep 2017 · 4 yrs 2 mos · Bengaluru Area, India

  • TMO Lead, Library characterization, PDK validation, verification and release management.
  • Physical Design Implementation.
  • STA Analyst.
  • DFX integration methodology definition,
  • Analog Circuit Simulation and characterization
  • Tool Development and support
  • Python, Shell, Perl, TCL and Skill automation.
Physical DesignPhysical VerificationStatic Timing AnalysisPerl AutomationTCLpython scripting+10

Physical Design Engineer

Apr 2009 – Jun 2013 · 4 yrs 2 mos · Bengaluru Area, India

  • Block level and IP level PD Implementation Lead
  • Mixed Signal Integration Lead.
  • Physical Design methodology definition.
  • IP Sign off / Tape out.
  • Custom Layout Design.
  • Perl and TCL automation.
Place & RoutePhysical DesignCustom Layout DesignReliability VerificationFloorplanningVLSI methodology+18

Senior ASIC Digital Design Engineer

Promoted

Mar 2007 – Sep 2017 · 10 yrs 6 mos · Bengaluru Area, India

  • Physical Design implementation.
  • ASIC Design methodology definition.
  • Sign-Off analyst and consultant.
  • Design Automation
  • Collateral management
  • Physical Verification methodology consultant.
  • Collateral QA implementation
Physical DesignPower DistributionStatic Timing AnalysisDFM MethodologyFloorplanningVLSI methodology+16

Physical Design Engineer

Mar 2007 – Apr 2009 · 2 yrs 1 mo · Bengaluru Area, India

  • Standard cell physical design and characterization
  • library architecture definition and methodology
  • Physical verification methodology
Place & RoutePhysical DesignShell ScriptingDesign Rule Checking (DRC)TCLPhysical Verification+2

Education

Manipal Academy of Higher Education

Master of Science - MS — Micro Electronics

Jan 2010 – Jan 2011

B. M. S. College of Engineering

Bachelor of Engineering - BE — Electronics and Communication

Jan 2005 – Jan 2008