May 2018 – Apr 2021 · 2 yrs 11 mos

• As RTL integrator worked on ARM IPs to integrate in SoC.

Jul 2016 – May 2018 · 1 yr 10 mos

• As part of SOC Design Team, I worked on Front End to Back End Hand off.
• As part of that I used design compiler to generate netlist from RTL and deliver to Back End.
• It also include to ensure the the quality of different inputs like RTL, clock constraints, exceptions, upf, scan insertion.

Jun 2015 – Jun 2016 · 1 yr

• As Design Engineer worked on STA, power fixes, RTL bug fixes.
• As Design Automation Engineer worked on tool development for timing review.

Dec 2012 – Mar 2013 · 3 mos · Greater Ahmedabad Area

• Daily O&M activities at for Vodafone Gujarat Circle.