Neha Tabassum — Software Engineer

7+ years of hands-on experience in front-end functional verification with expertise in module level verification closure using UVM methodology and top level verification using mixed methodology environments. • Proficiency in simulation tools and debug environments like Tanner Edit Tools, Anaconda Navigator, Synopsys VCS, Verdi tools, Questa, Visualizer, Manifest flow, Perforce, Methodics, and Jenkins. • Proficiency in hardware description languages like Verilog A, Verilog, RTL, System Verilog, UVM, C, C++. • Knowledge of different protocols like AXI, AHB, APB, MIPI -CSI, MIPI - DPHY. • Knowledge on PERL, TCL Scripting, Python. • Knowledge on circuit designing, layout designing, waveform debugging using Tanner Edit tools. • Hands on experience on using python for designing scripts for parameter extractions, fitting results. • Experience in creating and executing test plans, test cases, coverage metrics, bring-up of constrained, randomized and assertion based environment for module-level and top-level verification. • Understanding of digital logic and micro-architecture design principles. • Ability to debug and troubleshoot functional and performance issues in module-level and top-level verification environments. • Good communication and interpersonal skills for working collaboratively with cross-functional teams on module-level and top level verification tasks. • Leadership skills with experience in leading, mentoring, and training other engineers in module-level and top-level verification. Strategic thinking to align verification processes with module-level and top-level project objectives. • Verification methodology development experience to improve verification efficiency, quality, and reliability at both module-level and top-level. • Familiarity with industry-standard EDA tools such as Cadence, Synopsys. • Risk management skills to proactively identify and manage project risks in module-level and top-level verification environments.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC design and verification methodologies.

Experience: 8 yrs 4 mos