Bilwakeshwar Ivaturi — Software Engineer
8+ years of experience in Static Timing Analysis (STA), synthesis, and physical design on 2nm to 14nm technodes Experience in Starrc extraction and timing methodology. Worked on test chips with advanced technologies, including Gate-All-Around (GAA) and backside metal stack. Strong expertise in DFT constraints analysis and resolution. Proficient in Timing ECO, using tools such as Tweaker and PrimeTime DMSA. Fluent in English, Telugu, Kannada and Hindi.
Stackforce AI infers this person is a VLSI design expert with a focus on timing analysis and physical design.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 11 mos
Career Highlights
- 8+ years in Static Timing Analysis and physical design.
- Expertise in DFT constraints analysis and resolution.
- Proficient in Timing ECO using advanced tools.
Work Experience
Samsung Semiconductor
Senior Staff Engineer (1 yr 6 mos)
Qualcomm
Senior Lead Engineer (10 mos)
Senior Engineer (2 yrs 1 mo)
MediaTek
Staff Engineer (1 yr 3 mos)
Senior Engineer (1 yr 11 mos)
Engineer (11 mos)
IBM
Intern (5 mos)
Education
Master of Technology (M.Tech.) at International Institute of Information Technology Hyderabad (IIIT Hyderabad)
Bachelor of Technology (B.Tech.) at Mahatma Gandhi Institute of Technology
Intermediate at Sri Chaitanya Junior College
High School at Brilliant grammar high school