Dec 2019 – Sep 2022 · 2 yrs 9 mos · Hyderabad, Telangana, India

• Worked as embedded software engineer in Core Platform Team.
• Developed PCIe and MHI driver in QUALCOMM RTOS environment
• Designed and Developed the entire PCIe and MHI Low Power Modes design
• Working on access control driver which deals with XPU’s and SMMU configurations in tz
• Working on 4 wire Linux uart driver which is used as a transport layer for BT use case
• Involved in design level discussions with the HW POC’s and coordinating with cross functional teams during the development phase
• Porting SW code across multiple targets
• Performance matrix - Profiling SW/HW latencies
• Debugging many issues related to interrupts, suspend/resume, clocks, gpio’s and IO leakages
• Developing t32 test scripts to help in debugging
• Tech POC for the PCIe MHI protocol for my team
• Participating in multiple SOC bring-up activities
• Involved in pre-silicon activities, clocks, gpios, interrupts and design reviews
• Worked on many first time feature implementations in qualcomm
• Actively involved in code reviews and gave many tech presentations accross the team
• Mentoring Juniors/New joinees in the team

Jul 2017 – Dec 2019 · 2 yrs 5 mos · Bengaluru, Karnataka, India

• Worked as a software engineer in Foundry Design Services Team. I'm involved in Linux Device Driver development for ARM based SOC's.
• Developed PCIe Endpoint function driver for custom co-processor of mobile phone which is the only interface to communicate with the co-processor from the main processor. Includes interface functions for read/write, PCIe EDMA read/write, MSI/MSI-X Interrupt handling, PCIe ASPM & PM power management, AER error handling, Dynamic lane with and link speed change.
• Supported PCIe linkup and link down interrupts handling, system suspend to RAM and resume power management.
• Implemented PCIe initialization boot code which supports changing the lane width, link speed, BAR mask size, Equalization control settings and PHY tuning based on the OTP memory fused.
• Developed System Level Test driver using the proprietary software to verify the functionality of PCIe device during the mass production.
• Developed multi-threaded user space applications and handled many critical customer issues and production level issues.
• Actively collaborated with multiple teams across the organisation, Design Implementation and Design Verification teams during the pre-silicon phase of the SOC development.

Feb 2016 – Jun 2016 · 4 mos

• Worked as a Project Staff in the college for Design Innovation Center (DIC - MHRD).
• Developed an online examination evaluation tool using JAVA, MYSQL, Stanford NLP Tools.