Bhimender Saini — CEO

• 25 years of industry experience, 20+ successful tapeouts. Currently Senior Director of Engineering at Intel India, driving strategic vision and team leadership. • Demonstrated leadership in establishing a robust SoC design competency center in India, seamlessly integrating with global teams to drive excellence and innovation. • Expertise in collaborating with industry leaders and ecosystem partners to develop machinery and processes delivering predictable and high-quality tapeouts for complex SoCs Leadership and Management Experience o Global team management: Successfully Build and managed diverse, cross functional high performing teams (200+ engineers). Proficient in Operations, Talent and Budget management. Ensuring cost-effective, quality deliverables and creating a highly engaged and cohesiveness team environment. o Project Delivery: Proven track record in managing end-to-end project delivery for large-scale (600m2) projects. Defining and deploying processes, dashboards and KPIs for Project planning, control and proactive risk mitigation. o Stakeholder engagements: Strong connect with EDA, CAD-TFM team & Global Technical Workgroups. Build collaborative model to improvise on execution quality and efficiency. o Industry connects: Strong relationship with senior leaders, carries rapport for exceptional integrity and unwavering commitment. Known for saving and successfully delivering high-impact projects. Strategic Vision and Execution o Strategic Planning: Developed blueprint with 3x resource efficiency, aligning with the organization’s business objectives and industry trends. o Innovations & Optimization: Spearheading initiatives to introduce methodologies, tools, and technologies (e.g. AI enablement in APR & Signoff, workflow optimization in RTL handoff) to increase efficiency. o Inspirational leader: Inspiring and empowering teams to push boundaries and think beyond, driving both personal growth and organizational success. Technical Expertise o 25+ SoC Tapeout experience across Industry leading organizations. Expertise in design class from Smartphone (PPAS focus) to Server class (Reticle size, multi-level hierarchical design) on advanced nodes. o Strong understanding of complete design flow and interdependencies (RTL, DV, DFT, Post Silicon) with deep expertise in Physical design (Synthesis, PnR, Low power, Timing, and Power optimization). o Headed technical initiatives with EDA and CAD teams to develop & deploy methodologies and solutions (MS-CTS, TIP, IO budgeting, etc…) needed for design convergence of complex designs architectures.

Stackforce AI infers this person is a leader in semiconductor engineering with extensive experience in SoC design and project management.

Location: Bengaluru, Karnataka, India

Experience: 27 yrs 2 mos