Feb 2025 – Feb 2026 · 1 yr · Hyderabad, Telangana, India · On-site

• Contributed to the development of secure boot and platform security features across AMD Versal and Versal Gen platforms.
• Resolved change requests related to secure boot flow and Azure Key Vault key unwrap issues.
• Owned end-to-end CAVP certification for AES, RSA, ECDSA, DRBG, and SHA (SHA-2, SHA-3) algorithms, ensuring NIST-compliant cryptographic algorithm implementation.
• Addressed MISRA-C and Coverity findings to ensure secure and compliant firmware development.

Jan 2023 – Feb 2025 · 2 yrs 1 mo · Gurugram, Haryana, India · On-site

• Enhanced security in aerospace applications on Xilinx Ultrascale+ MPSoC by configuring the Memory Management Unit (MMU) for the Armv8 architecture, including setting up the required registers and writing assembly instructions for the Arm A53 cores specifically for bare metal mode, while ensuring the application maintained correct functionality in Linux mode.
• Achieved equivalent functionality on Arm R5 cores by configuring the Memory Protection Unit (MPU) for the Armv7 architecture. This involved setting up necessary registers and writing assembly instructions tailored for
• the Arm R5 cores.
• Handled exceptions for incorrect memory access (non-shared addresses) by studying the Armv8 (A53) and Armv7 (R5) architectures and implementing necessary measures for both core types.
• Successfully resolved memory access issues by implementing exception handling for the Arm A53 and R5 cores, ensuring robust system performance.