U

uday perumbuduri

Product Engineer

Hyderabad, Telangana, India15 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Timing Closure.
  • Led multiple successful tapeouts in deep submicron technologies.
  • Continuous learner focused on skill improvement.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and VLSI.

Contact

LinkedIn

Skills

Core Skills

Physical DesignVlsiTiming Closure

Other Skills

P&RSTASIPVFloorplanPlacementCTSOptimizationRoutingPlace & RouteScriptingTimingPrimetimeLow-power DesignTCL

About

- Hands on using ICC,PT and Encounter tools. - Experience in 3 tapeouts in deep submicron technologies 28nm TSMC process. - Expertise in P&R, STA,SI and PV. - Always on the look to improve skills and grow with the organization

Experience

15 yrs 9 mos
Total Experience
7 yrs 9 mos
Average Tenure
8 yrs 1 mo
Current Experience

Cadence design systems

Sr principal Design engineer

Apr 2018 – Present · 8 yrs 1 mo · India · On-site

P&RSTASIPVPhysical DesignVLSI

Amd

Consultant

Sep 2010 – Mar 2018 · 7 yrs 6 mos · Hyderabad Area, India

  • Part of 3 successfull tapeouts in AMD.
  • Carried out block level floorplan, placement, CTS, optimization, routing, timing closure.
FloorplanPlacementCTSOptimizationRoutingTiming Closure+1

Soctronics

P&R Engineer

Jul 2010 – Mar 2018 · 7 yrs 8 mos · Hyderabad Area, India

Education

VEDA IIT

MS — VLSI

Jan 2009 – Jan 2011

VREC

Bachelor of Technology (B.Tech.) — Electronics & Communications

Jan 2005 – Jan 2009