Saikat Senapati

Senior Software Engineer

Bengaluru, Karnataka, India17 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led flagship 5G solutions for Tier-1 operators
  • Contributed to NTIA 5G Challenge win
  • Award-winning ideas in hardware-in-loop 5G development
Stackforce AI infers this person is a Telecommunications Architect with expertise in wireless communication and signal processing.

Contact

Skills

Core Skills

Wireless TechnologiesPhysical Layer

Other Skills

AlgorithmsDebuggingLTEDigital Signal Processors3GPPRTOSEmbedded SystemsEmbedded SoftwareCARMLayer 1SoCDevice DriversEmbedded CReal-Time Operating Systems (RTOS)

About

I am a Senior Technical Architect with 16+ years of experience in wireless communication and digital signal processing, specializing in physical layer (L1) design, development, and optimization for LTE and 5G NR (SA & NSA) platforms. Throughout my career, I have led end-to-end delivery of flagship 5G solutions for Tier-1 operators, driving innovation in PHY algorithms and integrating ORAN-based deployments. My work has contributed to Radisys’ NTIA 5G Challenge win, multiple field trial successes, and the launch of carrier-grade 5G NR GA releases. I am passionate about leading cross-functional teams, solving complex technical challenges, and building high-performance wireless systems. My contributions include multiple granted patents, award-winning ideas like the hardware-in-loop 5G development model, and industry recognitions including Radisys LEGENDS 2021, Freescale Diamond Chip Award for small cell commercialization on on Freescale BSC9132 SoC and multiple performance recognitions across Radisys, Freescale, MediaTek and Tata Elxsi Ltd. Always exploring cutting-edge wireless technologies, I thrive on translating innovative ideas into scalable and commercialized solutions.

Experience

17 yrs
Total Experience
3 yrs 4 mos
Average Tenure
7 yrs 1 mo
Current Experience

Radisys corporation

2 roles

Senior Software Architect

Dec 2021Present · 4 yrs 5 mos

Software Architect

Mar 2019Nov 2021 · 2 yrs 8 mos

Parallel wireless

Member of Technical Staff at Parallel Wireless

Jun 2017Mar 2019 · 1 yr 9 mos · Bengaluru, Karnataka, India

  • Parallel Wireless is re imagining the RAN and building solutions that will enable and
  • accelerate long-term transition from today’s 4G LTE to tomorrow’s 5G cellular
  • networks. Converged Wireless System (CWS) is a high-capacity, 3GPP-compliant, multi-
  • RAT node (2G, 3G, 4G & 5G) that leverages the latest silicon to deliver reliable and cost-
  • effective coverage anywhere outdoor and in-vehicle.
  • Responsibilities:
  • Worked in LPPA feature where developed new algorithm to estimate TA with 2Ts
  • resolution using PRACH.
  • Worked extensively on internal and customers JIRAs for 4G PHY FDD/TDD.
AlgorithmsWireless TechnologiesPhysical LayerDebugging

Mediatek

Staff Engineer

May 2015May 2017 · 2 yrs · Bangalore

  • Responsibilities:
  • WCDMA RAKE receiver firmware development and maintenance.
  • RAKE DVT bring up of any new chip at onsite location.
  • Porting of RAKE architecture for CDMA 2000 with required algorithm changes.
  • Involved at different stages of RAKE firmware testing.

Freescale semiconductor

Senior Design Engineer

Nov 2011May 2015 · 3 yrs 6 mos · Noida, Uttar Pradesh, India

  • LTE eNodeB femtocell is a small cellular base station, typically designed for use in a home or small business. It connects to the service provider’s network via broadband. A femtocell allows service providers to extend service coverage indoors, especially where access would otherwise be limited or unavailable.
  • Responsibilities:
  • 1) Development and optimization of LTE eNB PUCCH signal chain on Freescale PSC913x SOC.
  • Implemented new algorithm for PUCCH format 2/2a/2b SINR computation which is less prone to errors with respect to timing advance. Worked on the power control calibration for control channel perspective. System Integration of PUCCH and tested with commercial UE and SMU. Worked on the 3GPP compliance verification for PUCCH
  • 2) Optimization of LTE eNB PRACH signal chain on Freescale PSC913x SOC.
  • 3) Developed FAPI compliant L1-L2 message flow for PUSCH on Freescale B3421 soc.
  • 4) Experience in working with Freescale FAE’s and handling various customer related issues, provided solutions to their requirements in hard time line.
  • 5) Worked with 3rd party vendor to integrate their L2 stack with Freescale L1.
  • 6) Provided design and source code training to various Freescale customers on eNB-L1 for PUCCH and PRACH modules.
  • Paper publication on PUCCH SINR algorithm in IEEE conference in ICACCS-2015
AlgorithmsWireless TechnologiesPhysical LayerDebugging

Tata elxsi

Design & Development Engineer(Wireless Domain)

Mar 2009Nov 2011 · 2 yrs 8 mos · Bangalore and Chennai

  • LTE UE layer1 development is part of the 3GPP release 8 specifications as well on COMMAGILITY Platform AMC3C87F3 which has three TI Faraday DSPs and each DSP has three TCI6487 processors.
  • Responsibilities:
  • 1) Design and development of LTE UE layer 1 signal chain and framework for PUCCH on TI Faraday DSP.
  • 2) Development of LTE UE layer 1 signal chain for PUSCH on TI Faraday DSP. Development of uplink transmitter Multi user MIMO, frequency hopping and Open Loop power control.
  • 3) Optimization of LTE UE Layer1 PUSCH modules : Channel Estimation and Equalization
  • Development platform: CCS v3.3, TI DSP BIOSv5.33, TMS320TCI6487.
  • Represented company’s top level customer at Mobile World Congress 2011 at Barcelona, Spain where I demonstrated our latest stack for femtocell solution

Education

West Bengal University of Technology, Kolkata

B-Tech — Electronics & Communication

Jan 2004Jan 2008

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