Feb 2017 – May 2019 · 2 yrs 3 mos · Bengaluru, Karnataka, India

• Data Fabric Diagnostic Development for APU/GPU/Servers Technology: C & C++
• Producer consumer Scenarios – verified x86 write ordering semantics by generating traffic using core coherent masters and IO coherent masters on different memory types, Bus Lock Conditions.
• Contended Lock Acceleration – SW Diagnostics of this feature - using semaphores/atomic locks for multiple threads accessing the same cache line impact perf of the application invoking it.
• Request Priority and Priority Pickers – Wrote test cases to elevate priority of certain type of requests for QoS purposes and verified that they are serviced properly without affecting ordering conditions.
• Component Harvesting and System Stressing – Wrote tests cases to disable a component in the fabric and verified that disabled component is guaranteed to not adversely impact data fabric performance.
• Coherency, System Probe Filter, SPF lookup – Understanding of caching mechanisms, directory lookup, probe and probe response generation to and from the fabric to cores
• Data Combining (Read/Write Combine) and Data Forwarding (Write to Read, Read to Read) – Wrote test cases to verify each pattern using dedicated performance events for each.
• DF components – Understanding and Testing of different DF components (coherent/non-coherent masters and slaves, transport layers, cake)& internal structures (Request & Response queues, Request & Response data scheduler queues, Retag Buffer, WaitAck Buffer, ProbeReq queue)

Jan 2015 – Jan 2017 · 2 yrs · Bengaluru, Karnataka, India

• Memory Controller Software Diagnostics Development for CPU & GPU Products: C & C++
• GDDR Trusted Memory – Verified Read and Write accesses to local and remote SFBM(Secure Frame Buffer Memory Regions) from Secure and Unsecure Clients.
• DRAM Temp Controlled SR(TCSR). Auto and Self Refresh, Per Bank, Per All Bank Refresh Signals
• Arbitration Policies - Open Page, Closed Page, Thresholding, Starvation Avoidance Policies.
• Ordering of Requests for Quality of Service – RAW, WAW & RAR and Memory Barriers
• Address Mapping for different Memory Channel Configurations & Interleaving – Populating DRAM Base and Limit Addresses correctly with interleaving bits set correctly.
• SW Design & Testability of Early Page Activation Policies for Application Performance Improvement

Oct 2013 – Dec 2016 · 3 yrs 2 mos · Bengaluru, Karnataka, India

• IOMMU Diagnostics Development & Virtualization for Servers/APU Technology: C & C++
• IOMMU Data Structures Library Development- Device Tables and Device Table Entries, Command Buffers, Event Buffers, PPR Log Buffers, Host and Guest Page Tables, Interrupt Tables.
• Address Translation & Protection- GPA->SPA - DMA from device(dGPU/iGPU) to System Memory
• Guest and Nested Address Translations – Verification of Guest Virtual to Guest Physical Address (PA) Translation to System PA using DMA from Virtual Machine to System Memory (GVA->GPA->SPA)
• Cache maintenance on both IOMMU and Device side – Translation Lookaside Buffer (TLB) – IOMMU local cache, I/O Translation Lookaside Buffer (IOTLB)
• Command Buffers (single/dual), Different IOMMU Commands, Ordering Rules – Completion Wait, Invalidate Device Table Entry, Invalidate IOMMU Pages, Invalidate IOTLB Pages, Invalidate Interrupt Table, Prefetch IOMMU Pages, Invalidate IOMMU All, Complete PPR Request.
• Event Buffers (single/dual), Different Events, Data Validation Sequence– Illegal Device Table Entry, IO Page Fault, Device Table Hardware Error, Invalid Device Request, Invalid PPR Req.
• Peripheral Page Request (PPR) and PPR Logging (single/dual PPR log buffers) – Use of ATS (Address Translation Service) with PRI (Page Request Interface) or PPR. Overflow protection using PPR Auto Response, PPR Log Dual Buffering, PPR Log Overflow Early Indication, PPR Auto Response.
• Interrupt Remap Virtualization using Guest Virtual APIC Interrupt Controller – Device interrupt delivery to the running guest virtual machines without hypervisor intervention when interrupts virtualized.
• Multiple IOMMU’s – Supporting multiple IOMMU & various feature testing on server products.
• Cache Coherency and Input-Output Devices

Apr 2011 – Sep 2013 · 2 yrs 5 mos · Bengaluru, Karnataka, India

• PCIE Diagnostic Development Technology: C & C++
• Development of PCIE Controller diagnostics for Detection, Speed & Link width switching for SSD
• Detecting Bridge Device & Endpoints using PCIE Config Space, Enumeration
• PMC(Performance Monitor Counter) Tool development for all the IPs Technology: C & C++
• Developed this common tool across IPs to measure specific critical performance criteria
• Validation of Gating of clocks inside Scalable Data Fabric by comparing with always-on clock
• Wrote API’s for measuring various events of IOMMU, IOHC, Data Fabric, Memory, SDP, IOAPIC