Rujuta Vaze

Software Engineer

San Jose, California, United States3 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in formal verification and RTL design.
Proven track record in optimizing hardware performance.
Strong background in FPGA and digital hardware design.

Stackforce AI infers this person is a Semiconductor and Electronics expert with a focus on digital hardware design and verification.

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Skills

Core Skills

Computer ArchitectureRtl VerificationFormal VerificationDigital Hardware Design

Other Skills

SystemVerilogDatapath VerificationFormal Coverage AnalysisVC Formal Datapath VerificationVC Formal Property VerificationPCB DesignArduinoOpenCLFPGADebuggingTCLScriptingAssertion Based VerificationUPFFunctional Verification

Experience

3 yrs 11 mos

Total Experience

1 yr 11 mos

Average Tenure

3 yrs 5 mos

Current Experience

Amd

3 roles

Senior Silicon Design Engineer

Promoted

Mar 2025 – Present · 1 yr 3 mos

Silicon Design Engineer 2

Jan 2023 – Mar 2025 · 2 yrs 2 mos

SystemVerilogComputer Architecture

CPU cores RTL design and verification Intern

May 2022 – Aug 2022 · 3 mos · United States

Performed Formal Coverage Analysis of the CT unit of the CPU architecture.
VC Formal Datapath Verification of the EX unit of CPU core to expose bugs in the RTL design and debugging using Verdi tool.
VC Formal Property Verification of sub-modules of EX unit to verify control paths.

RTL VerificationDatapath Verification

Tantrayut telecommunications pvt ltd

Graduate Engineer

Jan 2021 – Jul 2021 · 6 mos

Designed PCB schematics and layout to control six actuators of Stewart Platform in six degrees of freedom using Arduino DUE.
Performed thorough testing of hardware using oscilloscope and multimeter.
Developed optimization routine to achieve optimal constructional parameters of Stewart Platform.

National centre for radio astrophysics

Research Intern

May 2019 – Jul 2019 · 2 mos · Pune

Implemented real-complex FFT for Pulsar signals data from GMRT on NallaTech Arria A10 FPGA board using OpenCL, a high-level synthesis implementation.
Achieved 9% reduction in Energy Consumption (27 Watts) and high performance (3.7 GFLOPS/Watt) as compared to that of GPU P100 (250 Watts and performance of 2 GFLOPS/Watt) and proved that FPGA is highly energy-efficient.