Davinder Kumar

CEO

Bengaluru, Karnataka, India22 yrs 11 mos experience

Highly Stable

Key Highlights

23+ years of experience in SoC/IP FE design and DV.
Led successful silicon-proven tape-outs in chip development.
Certified Project Management professional with global team leadership.

Stackforce AI infers this person is a semiconductor and ASIC design expert with extensive experience in AI hardware and chip development.

Contact

Skills

Other Skills

Engineering ManagementDebuggingMixed SignalVery-Large-Scale Integration (VLSI)SemiconductorsField-Programmable Gate Arrays (FPGA)VerilogVHDLEmbedded SystemsFunctional VerificationSpecmanStatic Timing AnalysisRTL verificationSystemVerilogTiming Closure

About

Accomplished expert in SoC/IP FE design and DV with 23+ years of experience with deep understanding of system design and architecture Spearheaded the soft IP RTL design and DV team, assuming full ownership and strategic direction of a large-scale 5G IP portfolio. Delivered exceptional results leading cross-domain projects in Data Centric AI server CPU’s, wireless, wireline, automotive, and IoT’s. Highly experienced ASIC expert with end-to-end expertise in chip development (RTL2GDSII), driven multiple successful silicon-proven tape-outs. Certified Project Management professional, delivering high-profile chip tape-outs with expertise in technical excellence, timelines, and global team leadership.

Experience

22 yrs 11 mos

Total Experience

7 yrs 6 mos

Average Tenure

3 mos

Current Experience

Amd

Engineering Leadership

Feb 2026 – Present · 3 mos · Greater Bengaluru Area · Hybrid

AI hardware data acceleration!

Proxelera

Vice President engineering/Chip Lead

Aug 2024 – Dec 2025 · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

Chip Lead, Custom Silicon Design
Led the hands-on technical architecture, definition, design, and development of AMS Custom Ultra-Low Power ASICs. Drove the entire chip lifecycle, from initial specification to final part delivery, managing requirements, resources, stakeholders, and customer interactions end-to-end.

Intel corporation

5 roles

Engineering leadership

Promoted

May 2020 – Jul 2024 · 4 yrs 2 mos

Technical hands-on:
At Intel Data centric AI server domain
Led SOC FE Design/DV architecture
Led Post Silicon Debug for Xeon Server

Engineering Manager/Tech-lead

Promoted

Jan 2015 – Apr 2020 · 5 yrs 3 mos

Managed and technically led the HW IP RTL design and DV team within Intel 5G modem division, complete ownership of IP portfolio and roadmap of design and development/planning/execution and different deliverables to the various SoC pre/post silicon support across Intel.
Led pre-silicon digital & MixSignal IP & SoC Design activity.
Managed Offshore Development Centers with complete technical aspects including task assignment, progress tracking, financial, infrastructure and other supports.

Member Technical Staff - MTS

Promoted

Feb 2011 – Feb 2015 · 4 yrs

RTL design & verification, technical project management of different HW & NoC subsystem and IP designs including image signal processing, security, connectivity and diffrent bus protocols.

Staff Engineer(Infineon wireless 5G)

Jan 2007 – Jan 2011 · 4 yrs

Pre-silicon HW design & verification lead DV architect.

Chip Lead (Infineon wireless 5G)

Oct 2005 – Jan 2010 · 4 yrs 3 mos

Chip lead for multiple silicon proven ASIC designs with the complete ownership of frontend/backend design activity RTL2GDSII. Well versed and hands-on full asic design cycle from R2G, PD, timings, eco’s etc.

Lsi, an avago technologies company

Design Engineer

Jan 2003 – Sep 2005 · 2 yrs 8 mos · Dubai Silicon Oasis(DSO) · On-site

Fullchip asic design flow qualification with Texas Instruments bangalore.
Digital intigrated TV subsystem FE RTL verification and flow automation with LSI Logic Dubai Design Centre, deputed from Tata Elxsi