Vishal Jain — Software Engineer

Experienced RTL Design Engineer with a strong background in micro-architecture design, RTL implementation using Verilog/System Verilog and post-silicon validation. Passionate about designing high-performance and efficient digital systems, I have worked extensively with front-end EDA tools and have contributed to SSD controller design, address caches (TLB), and various memory subsystem concepts. In addition to RTL design, I have developed multiple Python scripts for bug-free RTL generation, streamlining design efficiency and ensuring high-quality hardware. I have also built Python-based automation in financial markets, implementing scripts for automatic trading. With a Bachelor's degree in Electronics and Communication Engineering from NIT Warangal, I thrive in solving complex design challenges and optimizing hardware for performance, power, and area. Constantly driven by innovation, I enjoy collaborating with cross-functional teams to push the boundaries of what’s possible in consumer electronics. Let’s connect and discuss cutting-edge developments in hardware design and automation!

Stackforce AI infers this person is a Digital Systems Engineer with expertise in RTL design and automation in consumer electronics.

Location: Udaipur, Rajasthan, India

Experience: 10 yrs 7 mos