Deepak Sharma

Platform Engineer

Bengaluru, Karnataka, India16 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Hardware Architecture and Signal Integrity.
Led cost reduction initiatives with significant impact.
Recipient of multiple recognition prizes for quality and delivery.

Stackforce AI infers this person is a Hardware Architect specializing in Electronics and Embedded Systems.

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Skills

Core Skills

Hardware ArchitectureSignal Integrity

Other Skills

DebuggingMotherBoard DesignElectronics Hardware DesignCAnalogEmbedded SystemsC++

Experience

16 yrs 6 mos

Total Experience

3 yrs 3 mos

Average Tenure

5 yrs 4 mos

Current Experience

Intel technology india pvt ltd

Platfom Hardware Architect (Reference Platform)

Jan 2021 – Present · 5 yrs 4 mos · Bengaluru · On-site

Currently working as Hardware System Architect and Design Lead for Intel Client Silicon
for Entry, Mainstream, Thin and Light PC Segment. Job role involves working with
various stakeholder like Silicon Segment Architect, Product Architect, Silicon and Platform
Validation Architect, Marketing, Packaging, Customer engagement etc., to define right
landing zone for Reference and Validation platform.
Also, responsible for building, architecting and designing the best in class, cost effective, quality reference and validation design to achieve faster TTM for Client Mobile Silicon.
Worked on various cost reduction initiative from N-1 platform re-use, BOM cost reduction,
PCB cost reduction and low-cost PCB vendor enabling.
Received DRA’s on PCB Panelization optimization through denser PCB desig. This also helps in Carbon Footprint Reduction.
Architected and Designed a low-cost FPGA based Debug Add in Card for
remote debug, monitoring, and faster root cause of any issue/instability of Reference and
Validation platform.
Architected a Universal Programming Hardware/Tool based on One GUI, One Tool for all programming requirement of PC Hardware.
Running WG which focus on PCB Characterization to ensure that Reference System Hardware meets all Signal Integrity requirement thereby avoiding
any HW issues which may gate faster Silicon TTM.
Conducts training and courses on Best Known practices, Basic of Signal Integrity, PCH
Architecture etc., for new hires.
Recipient of Multiple Department and Group Recognition Prize during this phase for cost reduction initiatives, remote automation of debug, Quality, On Time delivery, and root causing various issues across product lines.

Signal IntegrityDebuggingHardware ArchitectureMotherBoard DesignElectronics Hardware DesignC+3

Intel technologies india

PC Platform Hardware Design Lead

Jan 2017 – Dec 2020 · 3 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Worked as Design Lead for Multiple Reference and Validation platforms for Intel Mobile and
Halo Client PC Silicon across years.
These are reference validation platform used for SW Enabling, SOC Qualification (Both
Functional and Silicon Validation).
Worked with cross functional architects and across geo teams to create a platform landing
zone which meets all validation and screening requirement for SOC qualification and
serves as reference design for Intel customers.
Leads and Facilitated design development, program execution, milestone tracking and
unblocking if any issues, conducting reviews and helping in deployment plan across geos.
Supported Power On, Validation and critical debug related to platforms.
Recipient of Multiple Department and Group Recognition Prize during this phase for
Quality, On Time delivery, unblocking and root causing various issues across product lines.

Intel technology india pvt ltd

Hardware Engineer

Jan 2012 – Dec 2016 · 4 yrs 11 mos · Bengaluru Area, India · On-site

Design and Validation of Reference and Validation platform for Mobile, AIO, Halo and
Desktop SKU’s.
Owned interfaces like PCIe, Memory, TBT, Type C, USB, LAN, SATA, UART, I2C, SPI, EC,
GPIO’s etc.
Designed interposer to test N board with N-1 Silicon before delivering it for Power On with
intended N Silicon
Expertise in Intel CPU and PCH Architect and its various blocks.
Worked as a Customer Support Forum Lead for reference boards for Mobile, Halo and
Desktop Segment Platform. Played a pivotal role in debug and support of various platform
issues.
Worked closely with ODC and ODM design teams to Drive Design, Board Bring-
Up and Functional Testing for programs.

Bits, pilani

Teaching Assistant

Aug 2009 – Dec 2010 · 1 yr 4 mos · Pilani, Rajasthan

Worked as a Project Assistant in BITS-Pilani in ARC (Academic Registration and Counseling) Division and was associated with EEE (Electrical and Electronics) Department:-
 -Worked as an Instructor of Analog and Digital Electronics Lab.

Ceeri, pilani

Project Assistant

Jul 2008 – Jul 2009 · 1 yr · Pilani, Rajasthan, India.

Worked as a Project Assistant in HMG (Hybrid Micro-Circuit Group) at CEERI (Central Electronics Engineering Research Institute), Pilani. During the same, I was involved in E-tongue electrodes fabrication and establishment of lab for LTCC (Low Temperature Co Fired Ceramic) Technology.