Mahesh Kulkarni

CEO

Bengaluru, Karnataka, India25 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in power optimization for discrete graphics SOCs
  • Led multiple successful graphics IP delivery projects
  • Strong background in physical design and tapeout processes
Stackforce AI infers this person is a Semiconductor Engineering Expert with a focus on Power Optimization and Physical Design.

Contact

Skills

Core Skills

Physical DesignHigh Performance Computing (hpc)Power OptimizationPower EstimationServer Soc IntegrationProgram ManagementGraphics Ip DeliverySubsystem DeliveryClock Distribution Network

Other Skills

Place & RouteTapeoutPower Modeling

Experience

25 yrs 8 mos
Total Experience
5 yrs 10 mos
Average Tenure
2 yrs 2 mos
Current Experience

Amd

Power Lead core team

Mar 2024Present · 2 yrs 2 mos

Place & RouteHigh Performance Computing (HPC)TapeoutPhysical Design

Intel corporation

5 roles

Power Optimization, Estimation, Projections lead for Discrete Graphics SOCs

Promoted

Jan 2019Jun 2023 · 4 yrs 5 mos · Bengaluru, Karnataka, India · On-site

  • Responsible to drive and coordinate all pre-si power related activities across entire design cycle from project inception through tape-in
  • Lead the definition, methodology and tools/flows for SOC Power attainment/modeling for client and server discreate graphics SOCs including IP power modeling, power estimation/projection and end to end power attainment in a backend design cycle.
  • Identify opportunities for power improvements by bottom up data mining and profiling and enabling best in class low power design methods.
High Performance Computing (HPC)Physical DesignPower OptimizationPower Estimation

Engineering Manager, Server Design Group (SDG)

Jan 2016Jan 2018 · 2 yrs

  • Responsible for server SOC integration and program manager.
Place & RouteTapeoutServer SOC IntegrationProgram Management

Engineering manager, VPG

Jan 2009Jan 2016 · 7 yrs

  • Responsible for delivering Graphics IP for multiple generations of client products.
Place & RouteTapeoutGraphics IP Delivery

RLS Lead

Jan 2007Jan 2009 · 2 yrs

  • Responsible for delivering fully converged sub systems for multiple projects.
Place & RoutePhysical DesignSubsystem Delivery

Clock Lead

Jan 2002Jan 2006 · 4 yrs · Bangalore, India

  • Responsible for defining and implementing complete clock distribution network for multiple north bridge products.
Physical DesignClock Distribution Network

Stmicroelectronics

Sr design Engineer

Jan 1998Jan 2002 · 4 yrs

Physical Design

Education

Nagpur University

Master of Technology - MTech — Electronics

Jan 1996Jan 1998

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