Chandra P Joshi (CP)

Product Engineer

Bengaluru, Karnataka, India23 yrs 8 mos experience
Highly Stable

Key Highlights

  • 22+ years of chip design leadership experience.
  • Led architecture for multiple key Intel products.
  • Expertise in SoC architecture and microarchitecture.
Stackforce AI infers this person is a Semiconductor Architect with extensive experience in server and client chip design.

Contact

LinkedIn

Skills

Other Skills

SoC ArchitectureCoherent SubsystemsIO SubsystemsPerformance and PowerClient SoCServer DesignMicroarchitectureASICProcessorsVerilogVLSIComputer ArchitectureICRTL DesignSoC

About

A seasoned HW engineer with 22+ years’ experience of chip design leadership across Intel server and client product lines and lifecycles.  Led the architecture and microarchitecture teams of key products such as Brodwell-DE, Broadwell-NS, Alderlake-N and Jasperlake. A considerable contributor to Intel product lines.  Worked all levels of chip design life cycle; SoC architecture, microarchitecture, RTL design and drove PPA closures, pre-si and post-si validation.  Track record of defining new products engineering solution to meet business requirements.  Ability to visualize complexity of options and pick feasible solution that can fit in given guardrails.  Ability to technically lead teams and optimize work for team by right prioritization, setting direction in lake of data.  Deep dives in complex problem as required, assess gaps and complexity, and sensitizes & influence higher level leaders to make right decisions.  Core Technical Expertise o Servers and Client SoC micro-architecture, architecture, integration as showcased in many programs. o IO system Protocols and subsystems like PCIe, UPI and have rich history of solving problems around these. o Coherent and non-coherent protocols and fabrics as many features & flows has been proposed and handled.

Experience

23 yrs 8 mos
Total Experience
22 yrs
Average Tenure
1 yr 8 mos
Current Experience

Nvidia

Senior Architect

Sep 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

8 roles

Principal Engineer: Lead to redeem Next Gen Server Processor's IO Clusters

Jul 2022 – Aug 2024 · 2 yrs 1 mo

Principal Engineer: Lead Client N-Series CPU Architect (Alderlake-N)

Sep 2020 – Jul 2022 · 1 yr 10 mos

  • Lead architecture of Alderlake-N CPU SoC for Education, Essential & Chrome segment.
  • https://www.intel.com/content/www/us/en/products/docs/processors/intel-processor/n-series-brief.html
  • https://ark.intel.com/content/www/us/en/ark/products/231803/intel-processor-n100-6m-cache-up-to-3-40-ghz.html

Principal Engineer: Lead Server CPU Micro-Architect/Architect (Sapphire Rapids-EE)

Apr 2020 – Jul 2021 · 1 yr 3 mos

  • Lead Server CPU Architect focused to IOT and Networking.

Lead Client N-Series CPU Architect (Jasperlake)

Jan 2017 – May 2020 · 3 yrs 4 mos

  • Lead architecture of Jasperlake CPU for Education, Essential & Chrome segment
  • Intel® Pentium® Silver N600*, Intel® Celeron® Processor N450*, N510*
  • https://ark.intel.com/content/www/us/en/ark/products/codename/128823/jasper-lake.html
  • https://www.anandtech.com/show/16388/intel-launches-jasper-lake-tremont-atom-cores-for-all

Lead Server CPU Architect & Micro-architect (Xeon® D)

Promoted

Jan 2012 – Jan 2017 · 5 yrs

  • Defined and Led architecture of Intel's first networking focused Xeon-D Server Broadwell-DE-NS with integrated 40G Ethernet and QAT technology (Intel® Xeon® Processor D-15**N).
  • https://en.wikichip.org/wiki/intel/cores/broadwell_de
  • Xeon-D Series enabler by providing Intel's first Serer SoC solutions to integrate IPs and Led Micro-architect of Intel's first Xeon-D Server Broadwell-DE for Edge, Cloud & Storage segments (Intel® Xeon® Processor D-1500 Product Family).
  • https://www.intel.com/content/www/us/en/embedded/products/broadwell-de/overview.html

Micro-architect & Technical Lead Server CPU

Apr 2009 – Sep 2016 · 7 yrs 5 mos

  • Led Technical Forum for feature design making for Broadwell Xeon Server family products (Single & Multi Socket, Efficient Performance, Scalable Performance). Micro-architect lead of multiple building blocks integrated IO Hub (PCIe & Non Coherent blocks), Home Agent Coherence Controller, QPI stack etc. (Intel® Xeon® Processor E7-88**/48** E5-26**/16**)
  • https://ark.intel.com/content/www/us/en/ark/products/codename/38530/broadwell.html

Technical Lead Xeon Chipset (IOH)

Jan 2006 – Dec 2009 · 3 yrs 11 mos

  • Technical lead for Dual IOH microarchitecture for Boxboro/Tylersburg XEON chipset for in Nehalem/Westmere CPU and Intel's first coherent QPI Link. (Intel® X58 Express and X55*0 IO Hub)
  • https://ark.intel.com/content/www/us/en/ark/products/codename/28106/tylersburg.html

Design Lead and Micro-architect Xeon Server

Jul 2002 – Dec 2005 · 3 yrs 5 mos

  • RTL lead and micro-architect of coherence controller of Intel's first Xeon transition from FSB bus based group of discrete CPU+chipsets to uncore & QPI inception and Link based muti-socket Xeon Server CPUs.

First rain

Software Engineer

Jan 2002 – Jan 2002 · 0 mo

Lk global

Software Engineer

Jan 1995 – Jan 1995 · 0 mo

Education

Indian Institute of Technology, Delhi

M.S. (Research) — Computer Science

Jan 1999 – Jan 2002

Engineering College Kota

B.E. — Computer Science

Jan 1989 – Jan 1994