Sherin K Bose

Software Engineer

Bengaluru, Karnataka, India18 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

16 years of expertise in Analog/Memory Layout Engineering.
Proficient in low noise and low power data path design.
Strong track record in managing complete project operations.

Stackforce AI infers this person is a Semiconductor Layout Engineer with extensive experience in physical design and project management.

Contact

Skills

Core Skills

Physical DesignSemiconductors

Other Skills

Layout Versus Schematic (LVS)DRCPhysical VerificationVLSICadence VirtuosoC++Mixed SignalCMOSVery-Large-Scale Integration (VLSI)Design Rule Checking (DRC)

About

I am an accomplished professional with nearly 16 years of career success in Analog /Memory Layout Engineering. I have attained proficiency in developing, driving and implementing layout methodologies. My dexterity lies in designing low noise, low power data paths, memory blocks and Analog blocks. Demonstrated excellence in managing design engineering operations entailing required analysis, product design & development, process developments and technical evaluations. Over the time, I have proved my excellence in specifying new functional requirements towards designs, tests, and integration ..Track record of managing the complete project operations including planning, designing, resource utilization drawing review and so on. • I possess working excellence in o working with 4nm,5nm,7nm,10 nm ,14 nm,22nm,28nm, 32nm, 45nm, 65nm, 90nm & 130nm technologies o Noise Concepts Guard Ring, Shielding, Decoupling Caps and Matching Concepts like Gradient, Dummy, Common Centroid, Techniques & care for Analog/high speed cpu Memory Layout o Tools: Cadence Virtuoso Layout Editor / Virtuoso-XL, Mentor-Calibre

Experience

18 yrs 11 mos

Total Experience

4 yrs 8 mos

Average Tenure

13 yrs 6 mos

Current Experience

Qualcomm

Staff Layout Enginer

Dec 2012 – Present · 13 yrs 5 mos

Delivering the custom memory Macros/Compilers on time with all the quality
Acting as the main point of contact for many projects to SOC and providing support till final Sign-off from layout team
Working as the point of contact for 3rd party IPs to Qualcomm and set the right quality expectation and have regular interaction to assure the IPs are delivered with quality to SOC
Syncing project status with various site designers/chip teams Highlight risk/progress

Layout Versus Schematic (LVS)DRCPhysical DesignPhysical VerificationSemiconductorsVLSI+1

Incube solutions pvt ltd

Senior Layout Designer

Apr 2010 – Nov 2012 · 2 yrs 7 mos

• Delivered the memory/analog IP Macros given by the customer in on time with quality from onsite

Layout Versus Schematic (LVS)Physical Design

Arm

IO layout designer

Oct 2007 – Jan 2009 · 1 yr 3 mos

Delivered the physical design to the customer/test chip team with all the required data along with the physical design
Worked on 60 and 90 nm IBM nodes56

Layout Versus Schematic (LVS)Physical Design

Sankalp semiconductors pvt ltd

layout designer

Feb 2006 – Sep 2007 · 1 yr 7 mos

Delivered the entire project with quality from onsite/offsite
Coordinated the progress about the project to customer and managed the concepts of layout and circuit design

Layout Versus Schematic (LVS)