Asha Lata

Software Engineer

Bengaluru, Karnataka, India13 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and PnR implementation.
  • Proven track record in improving PPA in design flows.
  • Strong background in high frequency CPU designs.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and PnR.

Contact

LinkedIn

Skills

Core Skills

Physical DesignFloorplanningPlace & RouteTiming ClosureRouting

Other Skills

CTSHardware DesignClock Tree SynthesisCAD/CAMsignoffCrosstalkSTAstatic & dynamicLow-power DesignIRPowerplanningDRCsTeachingResearchPSpice

About

PNR and block level implementation floorplan , powerplan , placement , cts, routing , GDS-II, Physical verification. Drcs and LVS clean up . Congestion analysis with rectification IR analysis for both static and dynamic power . Power Grid analysis.

Experience

13 yrs 1 mo
Total Experience
2 yrs 7 mos
Average Tenure
4 yrs
Current Experience

Amd

Senior Silicon Design Engineer

Jun 2022 – Present · 4 yrs · Bengaluru, Karnataka, India

FloorplanningCTSPhysical Design

Cerium systems

Senior Physical Design Engineer

Apr 2021 – Jun 2022 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

  • Worked in Google as CAD engineer .
  • Create BOB flow and provided the flow and design solutions to multiple teams
  • Worked on PnR implementation with Improved PPA by improvement in PnR flow
Place & RouteHardware DesignPhysical Design

Intel corporation

Soc Design Engineer

Nov 2018 – Feb 2021 · 2 yrs 3 mos · Bengaluru, Karnataka, India · On-site

  • Worked on high frequency BIG CORE CPU designs .
  • Ownership of PNR implementation with timing closure and SignOff activities

Mirafra technologies

Physical Design Engineer

Jan 2015 – Feb 2016 · 1 yr 1 mo · Bengaluru, Karnataka, India · On-site

  • PNR and block level implementation floorplan , powerplan , placement , CTS, routing , GDS-II, Drcs and LVS clean up .
  • Congestion analysis
  • IR analysis for both static and dynamic power .
  • Power Grid analysis.

Pdm group of institutions

Assistant Professor (Electronics and Communication)

Apr 2010 – Nov 2014 · 4 yrs 7 mos · Haryana

  • Assistant Professor in Electronics and communication Department.
  • Part of Research and innovation in lower tech nodes in VLSI

Education

GITM Gurgaon campus

Master’s Degree — Electronics and Communications Engineering

Jan 2011 – Jan 2013

Maharshi Dayanand University

Bachelor’s Degree — Electronics and Communications Engineering

Jan 2006 – Jan 2009

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