Jey Vijayaraghavan

CTO

Bengaluru, Karnataka, India24 yrs 8 mos experience

Highly Stable

Key Highlights

24 years of experience in ASIC and FPGA industries.
Expert in Digital and Mixed Signal Verification.
Strong advocate for Diversity and Inclusion.

Stackforce AI infers this person is a leader in ASIC and FPGA design and verification.

Contact

Skills

Core Skills

Engineering ManagementEngineering Leadership

Other Skills

Director levelQuality ManagementVerification and Validation (V&V)Diversity & InclusionProblem Solving

About

Front end design and verification director with 24 years of industry experience across ASICS and FPGA. Led multiple IP design, verification and validation teams. Digital and Mixed Signal Verification are my forte. Known to introduce and drive out of the box solutions. Solving practical delivery/execution problems with a keen eye on quality. Have built teams from scratch and driven them towards excellence. GPTW advocate. D&I champion to the core.

Experience

24 yrs 8 mos

Total Experience

4 yrs 10 mos

Average Tenure

4 mos

Current Experience

Ericsson

ASIC Head, India

Jan 2026 – Present · 4 mos · Bengaluru, Karnataka, India · Hybrid

Leading the ASIC IP development team for Ericsson, India.

Altera

[Intel Spin-off] Director of Engineering

Jan 2025 – Dec 2025 · 11 mos · Bengaluru, Karnataka, India · On-site

Led transceiver/memory interface Soft IP verification and design teams.

Engineering ManagementDirector levelEngineering Leadership

Intel corporation

Director of Engineering

Oct 2015 – Dec 2024 · 9 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Owned Soft IP horizontal verification teams for Ethernet, Direct Phy, Memory and 5G IPs for the FPGA division before Altera Spin off. Owned all legacy Ethernet IP design for the same division.
Managed/Led a PCIE PHY verification team in the Mixed Signal IP division.
Managed/Led AXI, OCP and MNOC bridges in the core IP Group.

Engineering ManagementDirector levelEngineering Leadership

Microchip technology inc.

Verification Manager

Jul 2014 – Oct 2015 · 1 yr 3 mos

Owned SOC verification for a wireless + MIPS processor chip

Amd

Member of Technical Staff

Jul 2008 – Mar 2014 · 5 yrs 8 mos · Bengaluru, Karnataka, India · On-site

Led Cache, ESRAM and PLL Mixed Signal Verification teams
Program Managed the core development team for 1 product lifecycle

Cypress semiconductor corporation

Verification Lead

Mar 2001 – Jun 2008 · 7 yrs 3 mos · Nashua, New Hampshire, United States · On-site

Verification Engineer/Lead for Dual Port Memory and CPLDs
Design Engineer for a differential standard cell library: Circuit design, modeling and Layouts; Group Patent
Developed a statistical circuit optimization flow + toolbox