Apr 2024 – Nov 2024 · 7 mos

•  Site lead, Managing a team of 100+ engineers to deliver Imaging IP and SOC based on the imaging IP targeted for the Autonomous Mobile Robotic, Laptop and Automotive segments.
•  Highly competent and motivated team comprising of RTL, DFX, Verification, FPGA, Post Silicon validation engineers delivering quality Imaging IP and SOCs
•  Key Responsibilities include building team, retention in highly completive environment, quality project deliveries and smooth functioning of the organization

Feb 2021 – Mar 2024 · 3 yrs 1 mo

•  Site lead, Managing a team of 100+ engineers to deliver Imaging IP and SOC based on the imaging IP targeted for the Autonomous Mobile Robotic, Laptop and Automotive segments.
•  Highly competent and motivated team comprising of RTL, DFX, Verification, FPGA, Post Silicon validation engineers delivering quality Imaging IP and SOCs
•  Key Responsibilities include building team, retention in highly completive environment, quality project deliveries and smooth functioning of the organization

Nov 2018 – Jan 2021 · 2 yrs 2 mos

•  Managed a team of senior Micro-architects, chartered to deliver quality micro-architecture across Xeon/Xeon-D class of processors. Also, leading SOC RTL for Xeon-D segment of products
•  Managed a team of 70+ engineers : Architects, SOC Logic integration and SOC Validation to deliver Tape-Ins on highly complex Xeon class server chips
•  Delivered 3 Tape-in with high quality and on schedule
•  Responsible for driving a Xeon class server program from spec to Production : Working with cross functional teams – Post Silicon validation, Software, Manufacturing, Quality/Reliability teams to ensure delivery of the chip to customers

Feb 2017 – Aug 2017 · 6 mos · Bangalore

•  Led a mobility program on cutting edge Intel technologies on a highly complex 10nm project in Client space
•  Responsibilities included to drive chip from concept to production. Tracked schedule and manage risks
•  Led SOC and Post Si validation team : Design, Validation, Marketing, Manufacturing, Packaging and QnR teams

Mar 2016 – Feb 2017 · 11 mos · Bangalore

•  Led design and development of Imaging Co-processor for a high valued customer on TSMC process
•  Successfully taped out the Chip on schedule for this base product : Spec to Tapeout in 9 months
•  Led SOC cross functional team : Architecture, RTL, Design Verification, FPGA/Emulation, DFX and Physical design
•  Drove Platform level activities across Board development, S/W, Manufacturing and Packaging for Silicon readiness and Production

Aug 2017 – Oct 2018 · 1 yr 2 mos · Bangaon Area, India

•  Chartered with growing the Semiconductor business at Sasken
•  Responsibilities include : Grow the team capabilities / skillset, Work with Business lead/Sales team to win key customer business, Strategy for Semiconductor growth

Mar 2015 – Feb 2016 · 11 mos · Bangalore

•  Led development of Snapdragon processor program on leading edge technology node
•  Responsible for schedule and risks on the program. Key point of contact for SOC deliverables
•  Aligned all IP deliverables to ensure SOC needs are met. Drive mitigation plans and manage risks on the program
•  Presented weekly status and risks (along with mitigation plans) on the program to upper management

Sep 2014 – Feb 2015 · 5 mos

•  Drove Intel tablets in POS application to drive penetration in local market
•  Define POS feature working along with customer to ensure market needs are met
•  Drive the program from definition to completion including working with external outsource house. This includes industrial, electrical and system integration design

Dec 2011 – Aug 2014 · 2 yrs 8 mos

• Set strategic vision and direction for team, working with cross site management team in US to address the same. Ensure technical and management growth path for the organization
• Managing team of ~50 engineers delivering next generation Atom based SOC products intended for smartphone and tablet market
• Key responsibilities include : Resource management, project planning, risk assessment and mitigation plans, program management and customer enabling/debug

Aug 2011 – Dec 2011 · 4 mos

• Worked with Marketing and Platform team at Intel to define strategy, BOM cost reductions and Form Factor design
• Worked with multiple ODM’s to arrive at a cost effective solution for emerging markets. Delivered strategy for Emerging market low cost tablet
• Worked with system integrators to define and deliver s/w solutions for emerging market tablets

Mar 2009 – Jul 2011 · 2 yrs 4 mos

• Responsible for team vision and strategic direction. Built the team from 5 engineers to 30 in 9 months.
• Led a team of ~30 engineers to deliver pre-silicon verification on multiple CPU programs. Responsible for resource and project planning, verification scope, drive to schedule and quality, risk assessment and mitigation plans.
• Extensively worked with Design, architects, marketing to understand verification requirements for the market segment and tailor verification plans accordingly.
• Strong stakeholder management across cross-site teams in US and Israel.

Jan 2007 – Feb 2009 · 2 yrs 1 mo

• Responsible for production and launch of North bridge mobile chipset working with multiple cross-functional teams : marketing, design, validation, manufacturing and software
• Drove definition, schedules, and deliverables through the life cycle of the product. Dealt with customer facing issues and ensured resolution of the same in a prompt manner
• Responsible for alignment across the cross-functional team on resources, plans, schedule and risks

Jan 2006 – Dec 2006 · 11 mos

• Led a team of ~30 engineers to deliver pre-silicon verification on Mobile North Bridge chipset. Responsibilities included resource planning and management, deriving and maintaining schedule
• Additional responsibilities included driving efficient validation methodologies, tracking bugs, predicting bug trends and assess risk to tape-in

Mar 1998 – Dec 2005 · 7 yrs 9 mos

• Led Engineering Teams to deliver modules on mainstream Intel Desktop Chipsets on multiple products
• Responsibilities included resource planning, project execution, risk assessment and mitigation plans across design life cycle : RTL coding, pre-silicon verification, synthesis, timing closure, DFX and post silicon debug

Jul 1993 – Feb 1998 · 4 yrs 7 mos

• Various roles in RTL coding, pre silicon verification, synthesis, timing closure and DFX over the 5 year period
• Developed critical skills across the full product life cycle of ASIC development
• Owned and delivered scan insertion and ATPG flows for the group. First product at Intel to use industry standard tools for DFX flows